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authorJannis Harder <me@jix.one>2022-05-31 17:47:07 +0200
committerGeorge Rennie <georgerennie@gmail.com>2022-06-18 18:19:26 +0100
commite39c422734219bb0601827cb7c1d081f7ac7817b (patch)
tree6ddf17cbfe324654ea51f9127b3988edc326c5e2 /tests
parentc659bd18786633c52d42b5966627d39d99ae89e3 (diff)
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chformal: Test -coverprecond and reuse the src attribute
Diffstat (limited to 'tests')
-rw-r--r--tests/various/chformal_coverprecond.ys25
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/various/chformal_coverprecond.ys b/tests/various/chformal_coverprecond.ys
new file mode 100644
index 000000000..59e302a72
--- /dev/null
+++ b/tests/various/chformal_coverprecond.ys
@@ -0,0 +1,25 @@
+read_verilog -formal <<EOT
+module top(input a, b, c, d);
+
+ always @* begin
+ if (a) assert (b == c);
+ if (!a) assert (b != c);
+ if (b) assume (c);
+ if (c) cover (d);
+ end
+
+endmodule
+EOT
+
+prep -top top
+
+select -assert-count 1 t:$cover
+
+chformal -cover -coverprecond
+select -assert-count 2 t:$cover
+
+chformal -assert -coverprecond
+select -assert-count 4 t:$cover
+
+chformal -assume -coverprecond
+select -assert-count 5 t:$cover