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+read_verilog -formal <<EOT
+module top(input a, b, c, d);
+
+ always @* begin
+ if (a) assert (b == c);
+ if (!a) assert (b != c);
+ if (b) assume (c);
+ if (c) cover (d);
+ end
+
+endmodule
+EOT
+
+prep -top top
+
+select -assert-count 1 t:$cover
+
+chformal -cover -coverprecond
+select -assert-count 2 t:$cover
+
+chformal -assert -coverprecond
+select -assert-count 4 t:$cover
+
+chformal -assume -coverprecond
+select -assert-count 5 t:$cover