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| author | David Shah <dave@ds0.me> | 2019-09-11 13:55:16 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-09-11 13:55:59 +0100 |
| commit | c43e52d2d7d16c26b1a4a9c20fad83c9f4577910 (patch) | |
| tree | 0d49b02151e204e3f0365d604d50e7c152736005 /tests | |
| parent | c7f1368cd273f1d84507d29548f3420a08a82702 (diff) | |
| download | yosys-c43e52d2d7d16c26b1a4a9c20fad83c9f4577910.tar.gz yosys-c43e52d2d7d16c26b1a4a9c20fad83c9f4577910.tar.bz2 yosys-c43e52d2d7d16c26b1a4a9c20fad83c9f4577910.zip | |
Add equiv_opt -multiclock
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/equiv_opt_multiclock.ys | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/various/equiv_opt_multiclock.ys b/tests/various/equiv_opt_multiclock.ys new file mode 100644 index 000000000..81e36d018 --- /dev/null +++ b/tests/various/equiv_opt_multiclock.ys @@ -0,0 +1,12 @@ +read_verilog <<EOT +module top(input clk, pre, d, output reg q); + always @(posedge clk, posedge pre) + if (pre) + q <= 1'b1; + else + q <= d; +endmodule +EOT + +prep +equiv_opt -assert -multiclock -map +/simcells.v synth |