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| author | David Shah <dave@ds0.me> | 2019-09-11 09:57:30 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-11 09:57:30 +0100 |
| commit | c7f1368cd273f1d84507d29548f3420a08a82702 (patch) | |
| tree | e309451ee79c7329dc87457bdc08debfcd9bd8ab /tests | |
| parent | 486cbddd26a8db5bb2f2bbe3ea15e36b6c53a55e (diff) | |
| parent | 702ce405c18c2c28e7f5d354451141d8f16a4085 (diff) | |
| download | yosys-c7f1368cd273f1d84507d29548f3420a08a82702.tar.gz yosys-c7f1368cd273f1d84507d29548f3420a08a82702.tar.bz2 yosys-c7f1368cd273f1d84507d29548f3420a08a82702.zip | |
Merge pull request #1362 from xobs/smtbmc-msvc2-build-fixes
MSVC2 fixes
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/ice40/div_mod.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys index 21cac7144..821d6c301 100644 --- a/tests/ice40/div_mod.ys +++ b/tests/ice40/div_mod.ys @@ -4,6 +4,6 @@ flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_LUT4 +select -assert-count 59 t:SB_LUT4 select -assert-count 41 t:SB_CARRY select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D |