ABC9: Cell Port Bug Patch (#3670)

* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

---------

Co-authored-by: Eddie Hung <eddie@fpgeh.com>

2 files changed, 16 insertions, 0 deletions

diff --git a/tests/arch/xilinx/bug3670.v b/tests/arch/xilinx/bug3670.v
new file mode 100644
index 000000000..c7dd18079
--- /dev/null
+++ b/tests/arch/xilinx/bug3670.v
@@ -0,0 +1,13 @@
+module bug3670(input we, output [31:0] o1, o2, output o3);
+    // Completely missing port connections, where first affected port
+    // (ADDRARDADDR) has a $setup delay
+    RAMB36E1 ram1(.DOADO(o1));
+
+    // Under-specified input port connections (WEA is 4 bits) which
+    // has a $setup delay
+    RAMB36E1 ram2(.WEA(we), .DOADO(o2));
+
+    // Under-specified output port connections (DOADO is 32 bits)
+    // with clk-to-q delay
+    RAMB36E1 ram3(.DOADO(o3));
+endmodule
diff --git a/tests/arch/xilinx/bug3670.ys b/tests/arch/xilinx/bug3670.ys
new file mode 100644
index 000000000..772072c1e
--- /dev/null
+++ b/tests/arch/xilinx/bug3670.ys
@@ -0,0 +1,3 @@
+read_verilog bug3670.v
+read_verilog -lib -specify +/xilinx/cells_sim.v
+abc9