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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 17:26:25 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-11 17:26:25 -0800 |
commit | 79db12f238b2f8c5d547ea731a056f98d89bc4b9 (patch) | |
tree | 777a7b6e595ea9bdc97094380abcbb80b4cacf10 /tests | |
parent | 11128dccb53983e7bb784cf2514edcaa6eb822fb (diff) | |
parent | 04a2eb82045a658de22cea610a3ac8c5dee9333c (diff) | |
download | yosys-79db12f238b2f8c5d547ea731a056f98d89bc4b9.tar.gz yosys-79db12f238b2f8c5d547ea731a056f98d89bc4b9.tar.bz2 yosys-79db12f238b2f8c5d547ea731a056f98d89bc4b9.zip |
Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor
Diffstat (limited to 'tests')
-rw-r--r-- | tests/arch/ecp5/bug1459.ys | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/arch/ecp5/bug1459.ys b/tests/arch/ecp5/bug1459.ys new file mode 100644 index 000000000..1142ae0b5 --- /dev/null +++ b/tests/arch/ecp5/bug1459.ys @@ -0,0 +1,25 @@ +read_verilog <<EOT +module register_file( + input wire clk, + input wire write_enable, + input wire [63:0] write_data, + input wire [4:0] write_reg, + input wire [4:0] read1_reg, + output reg [63:0] read1_data, + ); + + reg [63:0] registers[0:31]; + + always @(posedge clk) begin + if (write_enable == 1'b1) begin + registers[write_reg] <= write_data; + end + end + + always @(all) begin + read1_data <= registers[read1_reg]; + end +endmodule +EOT + +synth_ecp5 -abc9 |