From 09841c2ac1f36d06faada27093a2cf0cdfb6cb42 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 15:35:26 -0700 Subject: Add quick-and-dirty specify tests --- tests/various/specify.v | 28 ++++++++++++++++++++++++++++ tests/various/specify.ys | 25 +++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 tests/various/specify.v create mode 100644 tests/various/specify.ys (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v new file mode 100644 index 000000000..aea0d0fc5 --- /dev/null +++ b/tests/various/specify.v @@ -0,0 +1,28 @@ +module test ( + input EN, CLK, + input [3:0] D, + output reg [3:0] Q +); + always @(posedge CLK) + if (EN) Q <= D; + + specify + if (EN) (CLK *> (Q : D)) = (1, 2:3:4); + $setup(D, posedge CLK &&& EN, 5); + $hold(posedge CLK, D &&& EN, 6); + endspecify +endmodule + +module test2 ( + input A, B, + output Q +); + xor (Q, A, B); + specify + //specparam T_rise = 1; + //specparam T_fall = 2; + `define T_rise 1 + `define T_fall 2 + (A => Q) = (`T_rise,`T_fall); + endspecify +endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys new file mode 100644 index 000000000..c4e901705 --- /dev/null +++ b/tests/various/specify.ys @@ -0,0 +1,25 @@ +read_verilog -specify specify.v +prep +cd test +select t:$specify2 -assert-count 0 +select t:$specify3 -assert-count 1 +select t:$specrule -assert-count 2 +cd test2 +select t:$specify2 -assert-count 1 +select t:$specify3 -assert-count 0 +select t:$specrule -assert-count 0 +write_verilog specify.out +design -stash gold + +read_verilog -specify specify.out +cd test +select t:$specify2 -assert-count 0 +select t:$specify3 -assert-count 1 +select t:$specrule -assert-count 2 +cd test2 +select t:$specify2 -assert-count 1 +select t:$specify3 -assert-count 0 +select t:$specrule -assert-count 0 +design -stash gate + +# TODO: How to check $specify and $specrule-s are equivalent? -- cgit v1.2.3 From bfb8b3018bbe2017ab35fbdc21813f69c56514bb Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 15:42:02 -0700 Subject: Fix spacing --- tests/various/specify.v | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index aea0d0fc5..68d3e33fc 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -14,15 +14,15 @@ module test ( endmodule module test2 ( - input A, B, + input A, B, output Q ); - xor (Q, A, B); + xor (Q, A, B); specify //specparam T_rise = 1; - //specparam T_fall = 2; - `define T_rise 1 - `define T_fall 2 - (A => Q) = (`T_rise,`T_fall); + //specparam T_fall = 2; + `define T_rise 1 + `define T_fall 2 + (A => Q) = (`T_rise,`T_fall); endspecify endmodule -- cgit v1.2.3 From 554c58715aa4f8f5ed9fb4293946ac420d3f67a2 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 3 May 2019 15:54:25 -0700 Subject: More testing --- tests/various/specify.v | 2 ++ tests/various/specify.ys | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.v b/tests/various/specify.v index 68d3e33fc..afc421da8 100644 --- a/tests/various/specify.v +++ b/tests/various/specify.v @@ -24,5 +24,7 @@ module test2 ( `define T_rise 1 `define T_fall 2 (A => Q) = (`T_rise,`T_fall); + //(B => Q) = (`T_rise+`T_fall)/2.0; + (B => Q) = 1.5; endspecify endmodule diff --git a/tests/various/specify.ys b/tests/various/specify.ys index c4e901705..87d98e0a0 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -5,7 +5,7 @@ select t:$specify2 -assert-count 0 select t:$specify3 -assert-count 1 select t:$specrule -assert-count 2 cd test2 -select t:$specify2 -assert-count 1 +select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 write_verilog specify.out @@ -17,9 +17,10 @@ select t:$specify2 -assert-count 0 select t:$specify3 -assert-count 1 select t:$specrule -assert-count 2 cd test2 -select t:$specify2 -assert-count 1 +select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 design -stash gate # TODO: How to check $specify and $specrule-s are equivalent? +# Otherwise, need more select statements to check parameter values are as expected? -- cgit v1.2.3 From 8c6e94d57c430fc516dbcfbde312dbd7c860477b Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 6 May 2019 12:26:15 +0200 Subject: Improve tests/various/specify.ys Signed-off-by: Clifford Wolf --- tests/various/specify.ys | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) (limited to 'tests') diff --git a/tests/various/specify.ys b/tests/various/specify.ys index 87d98e0a0..a5ca07219 100644 --- a/tests/various/specify.ys +++ b/tests/various/specify.ys @@ -8,10 +8,12 @@ cd test2 select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 +cd write_verilog specify.out design -stash gold read_verilog -specify specify.out +prep cd test select t:$specify2 -assert-count 0 select t:$specify3 -assert-count 1 @@ -20,7 +22,35 @@ cd test2 select t:$specify2 -assert-count 2 select t:$specify3 -assert-count 0 select t:$specrule -assert-count 0 +cd design -stash gate -# TODO: How to check $specify and $specrule-s are equivalent? -# Otherwise, need more select statements to check parameter values are as expected? +design -copy-from gold -as gold test +design -copy-from gate -as gate test +rename -hide +rename -enumerate -pattern A_% t:$specify3 +rename -enumerate -pattern B_% t:$specrule r:TYPE=$setup %i +rename -enumerate -pattern C_% t:$specrule r:TYPE=$hold %i +select n:A_* -assert-count 2 +select n:B_* -assert-count 2 +select n:C_* -assert-count 2 +equiv_make gold gate equiv +hierarchy -top equiv +equiv_struct +equiv_induct -seq 5 +equiv_status -assert +design -reset + +design -copy-from gold -as gold test2 +design -copy-from gate -as gate test2 +rename -hide +rename -enumerate -pattern A_% t:$specify2 r:T_RISE_TYP=1 %i +rename -enumerate -pattern B_% t:$specify2 n:A_* %d +select n:A_* -assert-count 2 +select n:B_* -assert-count 2 +equiv_make gold gate equiv +hierarchy -top equiv +equiv_struct +equiv_induct -seq 5 +equiv_status -assert +design -reset -- cgit v1.2.3