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| author | Jannis Harder <me@jix.one> | 2023-02-13 16:50:27 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-02-13 16:54:11 +0100 |
| commit | 55ad3fe6c701607ce6b184d03241be38e894c2fd (patch) | |
| tree | fd43f9e43ed82666e67c018a712b48e068f73378 /tests | |
| parent | 2a68eee5f164c1c028a386b090b63ca1e5ba5611 (diff) | |
| download | yosys-55ad3fe6c701607ce6b184d03241be38e894c2fd.tar.gz yosys-55ad3fe6c701607ce6b184d03241be38e894c2fd.tar.bz2 yosys-55ad3fe6c701607ce6b184d03241be38e894c2fd.zip | |
xprop tests: Make iverilog invocation more portable
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/xprop/test.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/xprop/test.py b/tests/xprop/test.py index 507e4e9e2..a275b0d93 100644 --- a/tests/xprop/test.py +++ b/tests/xprop/test.py @@ -357,15 +357,15 @@ for mode in ["", "_xprop"]: "-DSIMLIB_FF", "-DSIMLIB_GLOBAL_CLOCK=top.gclk", f"-DDUMPFILE=\"vsim_{expr}.vcd\"", + "-o", + f"vsim_{expr}", "verilog_sim_tb.v", f"vsim_{expr}.v", *simlibs, - "-o", - f"vsim_{expr}", ] ) with open(f"vsim_{expr}.out", "w") as f: - subprocess.check_call([f"./vsim_{expr}"], stdout=f) + subprocess.check_call(["vvp", f"./vsim_{expr}"], stdout=f) for mode in ["", "_xprop"]: if f"sim{mode}" not in steps: |