diff options
| author | Jannis Harder <me@jix.one> | 2023-02-13 14:03:08 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-02-13 14:05:16 +0100 |
| commit | 2a68eee5f164c1c028a386b090b63ca1e5ba5611 (patch) | |
| tree | 8b21cf9e71f7d280357a9a347fa750724a64cc04 /tests | |
| parent | 9f20beb7dfd98e16771dba02600c68e4fa1505ed (diff) | |
| download | yosys-2a68eee5f164c1c028a386b090b63ca1e5ba5611.tar.gz yosys-2a68eee5f164c1c028a386b090b63ca1e5ba5611.tar.bz2 yosys-2a68eee5f164c1c028a386b090b63ca1e5ba5611.zip | |
xprop: Test fixes and abort on test failure
Use `$finish(0)` to silently exit even when using recent iverlog
versions. Run `write_verilog -noexpr` before `write_verilog` as the
latter can modify the design.
This also enables checking the tests results, as xprop should be in a
state where the existing tests pass.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/xprop/generate.py | 2 | ||||
| -rw-r--r-- | tests/xprop/test.py | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/xprop/generate.py b/tests/xprop/generate.py index 1018215b6..484f1661c 100644 --- a/tests/xprop/generate.py +++ b/tests/xprop/generate.py @@ -33,7 +33,7 @@ def add_test(name, src, seq=False): print( f"\t@cd {workdir} && python3 -u ../test.py -S {args.seed} -c {args.count}{seq_arg} > test.log 2>&1 || echo {workdir}: failed > status\n" f"\t@cat {workdir}/status\n" - # f"\t@grep '^.*: ok' {workdir}/status\n" + f"\t@grep '^.*: ok' {workdir}/status\n" , file=makefile, ) diff --git a/tests/xprop/test.py b/tests/xprop/test.py index df355e7dc..507e4e9e2 100644 --- a/tests/xprop/test.py +++ b/tests/xprop/test.py @@ -275,7 +275,7 @@ if "prepare" in steps: file=tb_file, ) - print(" $finish;", file=tb_file) + print(" $finish(0);", file=tb_file) print("end", file=tb_file) print("endmodule", file=tb_file) @@ -344,8 +344,8 @@ for mode in ["", "_xprop"]: read_rtlil wrapped{mode}.il chformal -remove dffunmap - write_verilog -noparallelcase vsim_expr{mode}.v write_verilog -noexpr vsim_noexpr{mode}.v + write_verilog -noparallelcase vsim_expr{mode}.v """ ) |