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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-26 08:51:11 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-26 08:51:11 -0700 |
| commit | 4f0cb3449573acb189e877407d7b19a5d140c9e7 (patch) | |
| tree | 7aa49a38e06a3dba641096066c3fc7f06a224217 /tests | |
| parent | 5db96b8aec7be2fb864d0f41ef21bb5168fa6b5c (diff) | |
| parent | 0dd850e6552a74430559ed63c3a9a67aa1c84512 (diff) | |
| download | yosys-4f0cb3449573acb189e877407d7b19a5d140c9e7.tar.gz yosys-4f0cb3449573acb189e877407d7b19a5d140c9e7.tar.bz2 yosys-4f0cb3449573acb189e877407d7b19a5d140c9e7.zip | |
Merge pull request #1136 from YosysHQ/xaig_ice40_wire_del
abc9: Add wire delays to synth_ice40
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions