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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-09-11 21:28:40 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | 205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60 (patch) | |
| tree | 0bf154f48f4fa73b15e74c8b49d9bb9ab5584d09 /tests | |
| parent | df7fe40529f7e0a26626ac1b0ed12acf66bb40d3 (diff) | |
| download | yosys-205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60.tar.gz yosys-205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60.tar.bz2 yosys-205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60.zip | |
Fix div_mod test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/xilinx/div_mod.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 52e536a7f..e1c4d6912 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -7,7 +7,7 @@ cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 -select -assert-count 13 t:LUT4 +select -assert-count 12 t:LUT4 select -assert-count 6 t:LUT5 select -assert-count 80 t:LUT6 select -assert-count 65 t:MUXCY |