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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-09-11 20:34:22 +0300 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-17 17:10:02 +0200 |
| commit | df7fe40529f7e0a26626ac1b0ed12acf66bb40d3 (patch) | |
| tree | ecff4bd3b99b431b67a54fd76ef42a59d7219b04 /tests | |
| parent | 7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a (diff) | |
| download | yosys-df7fe40529f7e0a26626ac1b0ed12acf66bb40d3.tar.gz yosys-df7fe40529f7e0a26626ac1b0ed12acf66bb40d3.tar.bz2 yosys-df7fe40529f7e0a26626ac1b0ed12acf66bb40d3.zip | |
Fix div_mod test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/xilinx/div_mod.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index cc00b1a27..52e536a7f 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 -select -assert-count 21 t:LUT2 +select -assert-count 23 t:LUT2 select -assert-count 13 t:LUT4 select -assert-count 6 t:LUT5 select -assert-count 80 t:LUT6 |