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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-11 13:00:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-11 13:00:36 -0700 |
| commit | 1f3003be7d464372b1c94d6b8e47ffa0d75de0d3 (patch) | |
| tree | 9ef0d31dbb639dd7297a68174fdcfa2f64f4b529 /tests/verilog | |
| parent | e5ce5a4fd532f35cf8dd625b97aa426e4661e119 (diff) | |
| download | yosys-1f3003be7d464372b1c94d6b8e47ffa0d75de0d3.tar.gz yosys-1f3003be7d464372b1c94d6b8e47ffa0d75de0d3.tar.bz2 yosys-1f3003be7d464372b1c94d6b8e47ffa0d75de0d3.zip | |
verilog: error out when non-ANSI task/func arguments
Diffstat (limited to 'tests/verilog')
0 files changed, 0 insertions, 0 deletions