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| author | Eddie Hung <eddie@fpgeh.com> | 2020-05-05 08:01:27 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-05-05 08:01:27 -0700 |
| commit | 004999218f52cd5a1308023a474ee608b842a5b7 (patch) | |
| tree | d3ebdb8b3f5301f829ad589a1eb94ee6783c6cb3 /tests/verilog | |
| parent | e936ac61ea223ca27c1b6eaf195cac66dd255602 (diff) | |
| download | yosys-004999218f52cd5a1308023a474ee608b842a5b7.tar.gz yosys-004999218f52cd5a1308023a474ee608b842a5b7.tar.bz2 yosys-004999218f52cd5a1308023a474ee608b842a5b7.zip | |
techlibs/common: more robustness when *_WIDTH = 0
Diffstat (limited to 'tests/verilog')
| -rw-r--r-- | tests/verilog/upto.ys | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/verilog/upto.ys b/tests/verilog/upto.ys index d87f4424e..2f3394761 100644 --- a/tests/verilog/upto.ys +++ b/tests/verilog/upto.ys @@ -2,4 +2,3 @@ read_verilog <<EOT module top(input [-128:-65] a); endmodule EOT -dump |