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| author | Zachary Snow <zach@zachjs.com> | 2021-02-25 15:53:55 -0500 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-03-01 12:28:33 -0500 |
| commit | 1ec5994100510d6fb9e18ff7234ede496f831a51 (patch) | |
| tree | 77c8403f0ece00ad1b42e2e91f86befe0f736cac /tests/verilog/unmatched_else.ys | |
| parent | b6904a8e5344fcd01c1a0feea281cd7d7bf0f210 (diff) | |
| download | yosys-1ec5994100510d6fb9e18ff7234ede496f831a51.tar.gz yosys-1ec5994100510d6fb9e18ff7234ede496f831a51.tar.bz2 yosys-1ec5994100510d6fb9e18ff7234ede496f831a51.zip | |
verilog: fix handling of nested ifdef directives
- track depth so we know whether to consider higher-level elsifs
- error on unmatched endif/elsif/else
Diffstat (limited to 'tests/verilog/unmatched_else.ys')
| -rw-r--r-- | tests/verilog/unmatched_else.ys | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/verilog/unmatched_else.ys b/tests/verilog/unmatched_else.ys new file mode 100644 index 000000000..413f413c3 --- /dev/null +++ b/tests/verilog/unmatched_else.ys @@ -0,0 +1,6 @@ +logger -expect error "Found `else outside of macro conditional branch!" 1 +read_verilog <<EOT +module top; +`else +endmodule +EOT |