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| author | Claire Xen <claire@clairexen.net> | 2022-02-11 16:03:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-11 16:03:12 +0100 |
| commit | 49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch) | |
| tree | d0f20b8def36e551c6735d4fc6033aaa2633fe80 /tests/verilog/macro_arg_tromp.sv | |
| parent | 90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff) | |
| parent | e0165188669fcef2c5784c9916683889a2164e5d (diff) | |
| download | yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.gz yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.bz2 yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.zip | |
Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'tests/verilog/macro_arg_tromp.sv')
| -rw-r--r-- | tests/verilog/macro_arg_tromp.sv | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/verilog/macro_arg_tromp.sv b/tests/verilog/macro_arg_tromp.sv new file mode 100644 index 000000000..a9c68a417 --- /dev/null +++ b/tests/verilog/macro_arg_tromp.sv @@ -0,0 +1,21 @@ +// Taken from: https://github.com/YosysHQ/yosys/issues/2867 + +`define MIN(x, y) ((x) < (y) ? (x) : (y)) +`define CEIL_DIV(x, y) (((x) / (y)) + `MIN((x) % (y), 1)) + +module pad_msg1 (input logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] x, + output logic [`MIN(512*`CEIL_DIV(64, 512), 64)-1:0] y); + assign y[63:0] = x; +endmodule + +module pad_msg2 (input logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] x, + output logic [((512*`CEIL_DIV(64, 512)) < (64) ? (512*`CEIL_DIV(64,512)) : (64))-1:0] y); + assign y[63:0] = x; +endmodule + +module top(...); +`define add(x) x + +input [3:0] A; +output [3:0] B; +assign B = `add(`add(3)A)A; +endmodule |