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| author | Claire Xen <claire@clairexen.net> | 2022-02-11 16:03:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-11 16:03:12 +0100 |
| commit | 49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch) | |
| tree | d0f20b8def36e551c6735d4fc6033aaa2633fe80 /tests/verilog/genvar_loop_decl_1.sv | |
| parent | 90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff) | |
| parent | e0165188669fcef2c5784c9916683889a2164e5d (diff) | |
| download | yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.gz yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.bz2 yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.zip | |
Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'tests/verilog/genvar_loop_decl_1.sv')
| -rw-r--r-- | tests/verilog/genvar_loop_decl_1.sv | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/verilog/genvar_loop_decl_1.sv b/tests/verilog/genvar_loop_decl_1.sv new file mode 100644 index 000000000..b503f75da --- /dev/null +++ b/tests/verilog/genvar_loop_decl_1.sv @@ -0,0 +1,18 @@ +`default_nettype none + +module gate(a); + for (genvar i = 0; i < 2; i++) + wire [i:0] x = '1; + + output wire [32:0] a; + assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0}; +endmodule + +module gold(a); + genvar i; + for (i = 0; i < 2; i++) + wire [i:0] x = '1; + + output wire [32:0] a; + assign a = {1'b0, genblk1[0].x, 1'b0, genblk1[1].x, 1'b0}; +endmodule |