Merge branch 'master' into clk2ff-better-names

1 files changed, 21 insertions, 0 deletions

diff --git a/tests/verilog/doubleslash.ys b/tests/verilog/doubleslash.ys
new file mode 100644
index 000000000..c41673ee5
--- /dev/null
+++ b/tests/verilog/doubleslash.ys
@@ -0,0 +1,21 @@
+read_verilog -sv <<EOT
+module doubleslash
+  (input  logic   a,
+   input  logic   b,
+   output logic   z);
+
+  logic \a//b ;
+
+  assign \a//b = a & b;
+  assign z = ~\a//b ;
+
+endmodule : doubleslash
+EOT
+
+hierarchy
+proc
+opt -full
+
+write_verilog doubleslash.v
+design -reset
+read_verilog doubleslash.v