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| author | Claire Xen <claire@clairexen.net> | 2022-02-11 16:03:12 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-11 16:03:12 +0100 |
| commit | 49545c73f7f5a5cf73d287fd371f2ff39311f621 (patch) | |
| tree | d0f20b8def36e551c6735d4fc6033aaa2633fe80 /tests/verilog/always_comb_latch_4.ys | |
| parent | 90b40aa51f7d666792d4f0b1830ee75b81678a1f (diff) | |
| parent | e0165188669fcef2c5784c9916683889a2164e5d (diff) | |
| download | yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.gz yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.tar.bz2 yosys-49545c73f7f5a5cf73d287fd371f2ff39311f621.zip | |
Merge branch 'master' into clk2ff-better-names
Diffstat (limited to 'tests/verilog/always_comb_latch_4.ys')
| -rw-r--r-- | tests/verilog/always_comb_latch_4.ys | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/verilog/always_comb_latch_4.ys b/tests/verilog/always_comb_latch_4.ys new file mode 100644 index 000000000..46b78801b --- /dev/null +++ b/tests/verilog/always_comb_latch_4.ys @@ -0,0 +1,17 @@ +read_verilog -sv <<EOF +module top; +parameter AVOID_LATCH = 0; +logic x, z; +assign z = 1'b1; +always_comb begin + logic y; + if (z) + y = 0; + for (int i = 1; i == AVOID_LATCH; i++) + y = 1; + x = z ? y : 1'b0; +end +endmodule +EOF +logger -expect error "^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process" 1 +proc |