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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:54:29 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:54:29 -0700 |
commit | e263bc249b905195120fbc074c6f80d03fb21cf8 (patch) | |
tree | fbd7945706f88391bfd0622d3c8dfa89cbf4f639 /tests/various/muxpack.v | |
parent | 887df8914c64220b9f306b7d21f199fa247224fd (diff) | |
download | yosys-e263bc249b905195120fbc074c6f80d03fb21cf8.tar.gz yosys-e263bc249b905195120fbc074c6f80d03fb21cf8.tar.bz2 yosys-e263bc249b905195120fbc074c6f80d03fb21cf8.zip |
Add nonexclusive test from @cliffordwolf
Diffstat (limited to 'tests/various/muxpack.v')
-rw-r--r-- | tests/various/muxpack.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/various/muxpack.v b/tests/various/muxpack.v index 41dfed396..f3c25db8d 100644 --- a/tests/various/muxpack.v +++ b/tests/various/muxpack.v @@ -153,3 +153,16 @@ always @* else o <= i[4*W+:W]; endmodule + +module cliffordwolf_nonexclusive_select ( + input wire x, y, z, + input wire a, b, c, d, + output reg o +); + always @* begin + o = a; + if (x) o = b; + if (y) o = c; + if (z) o = d; + end +endmodule |