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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 21:52:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 21:52:53 -0700 |
| commit | 9dca024a30e5f6cfb06e1abb584ce1320fb81f16 (patch) | |
| tree | ec29453bdd3347c97b8285a9fd3880a906bde77d /tests/various/abc9.ys | |
| parent | cec2292b0bac819568c3d982e544cbe0aff99cb8 (diff) | |
| download | yosys-9dca024a30e5f6cfb06e1abb584ce1320fb81f16.tar.gz yosys-9dca024a30e5f6cfb06e1abb584ce1320fb81f16.tar.bz2 yosys-9dca024a30e5f6cfb06e1abb584ce1320fb81f16.zip | |
Add tests/various/abc9.{v,ys} with SCC test
Diffstat (limited to 'tests/various/abc9.ys')
| -rw-r--r-- | tests/various/abc9.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys new file mode 100644 index 000000000..922f7005d --- /dev/null +++ b/tests/various/abc9.ys @@ -0,0 +1,14 @@ +read_verilog abc9.v +proc +design -save gold + +abc9 -lut 4 +check +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports miter + |