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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-27 20:54:29 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-11 13:34:10 +0200 |
| commit | fd7921776387a05edadcc90d1300670d49a73d68 (patch) | |
| tree | 84fb8ab2ff4c012b5dd24e8c3dcd5dace93474fb /tests/svtypes | |
| parent | b96eb888cc7518c20532ff688ec24b8b51f88f8e (diff) | |
| download | yosys-fd7921776387a05edadcc90d1300670d49a73d68.tar.gz yosys-fd7921776387a05edadcc90d1300670d49a73d68.tar.bz2 yosys-fd7921776387a05edadcc90d1300670d49a73d68.zip | |
Add v2 memory cells.
Diffstat (limited to 'tests/svtypes')
| -rw-r--r-- | tests/svtypes/logic_rom.ys | 2 | ||||
| -rw-r--r-- | tests/svtypes/typedef_memory.ys | 2 | ||||
| -rw-r--r-- | tests/svtypes/typedef_memory_2.ys | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys index 7b079c136..776d2e985 100644 --- a/tests/svtypes/logic_rom.ys +++ b/tests/svtypes/logic_rom.ys @@ -1,3 +1,3 @@ read_verilog -sv logic_rom.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=8 %i diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys index 93cf47bbe..d47ee9929 100644 --- a/tests/svtypes/typedef_memory.ys +++ b/tests/svtypes/typedef_memory.ys @@ -1,3 +1,3 @@ read_verilog -sv typedef_memory.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys index 854e554f3..bfebd05fc 100644 --- a/tests/svtypes/typedef_memory_2.ys +++ b/tests/svtypes/typedef_memory_2.ys @@ -1,4 +1,4 @@ read_verilog -sv typedef_memory_2.sv prep -top top dump -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i |