From fd7921776387a05edadcc90d1300670d49a73d68 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcelina=20Ko=C5=9Bcielnicka?= Date: Thu, 27 May 2021 20:54:29 +0200 Subject: Add v2 memory cells. --- tests/svtypes/logic_rom.ys | 2 +- tests/svtypes/typedef_memory.ys | 2 +- tests/svtypes/typedef_memory_2.ys | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'tests/svtypes') diff --git a/tests/svtypes/logic_rom.ys b/tests/svtypes/logic_rom.ys index 7b079c136..776d2e985 100644 --- a/tests/svtypes/logic_rom.ys +++ b/tests/svtypes/logic_rom.ys @@ -1,3 +1,3 @@ read_verilog -sv logic_rom.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=8 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=8 %i diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys index 93cf47bbe..d47ee9929 100644 --- a/tests/svtypes/typedef_memory.ys +++ b/tests/svtypes/typedef_memory.ys @@ -1,3 +1,3 @@ read_verilog -sv typedef_memory.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys index 854e554f3..bfebd05fc 100644 --- a/tests/svtypes/typedef_memory_2.ys +++ b/tests/svtypes/typedef_memory_2.ys @@ -1,4 +1,4 @@ read_verilog -sv typedef_memory_2.sv prep -top top dump -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i +select -assert-count 1 t:$mem_v2 r:SIZE=16 %i r:WIDTH=4 %i -- cgit v1.2.3