diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-02-21 13:09:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-21 13:09:47 +0100 |
| commit | 6d12c83d362c709f72e64eea2121b2cffc12ee8d (patch) | |
| tree | db9f4bbd23313bb58468e24d191e38713cc73e77 /tests/sva/sva_throughout.sv | |
| parent | 17583b6a2175bf509d6a233e5684a183af54f48c (diff) | |
| download | yosys-6d12c83d362c709f72e64eea2121b2cffc12ee8d.tar.gz yosys-6d12c83d362c709f72e64eea2121b2cffc12ee8d.tar.bz2 yosys-6d12c83d362c709f72e64eea2121b2cffc12ee8d.zip | |
Add support for SVA throughout via Verific
Diffstat (limited to 'tests/sva/sva_throughout.sv')
| -rw-r--r-- | tests/sva/sva_throughout.sv | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/tests/sva/sva_throughout.sv b/tests/sva/sva_throughout.sv new file mode 100644 index 000000000..7e036a066 --- /dev/null +++ b/tests/sva/sva_throughout.sv @@ -0,0 +1,19 @@ +module top ( + input clk, + input a, b, c, d +); + default clocking @(posedge clk); endclocking + + assert property ( + a |=> b throughout (c ##1 d) + ); + +`ifndef FAIL + assume property ( + a |=> b && c + ); + assume property ( + b && c |=> b && d + ); +`endif +endmodule |