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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-27 11:42:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-27 11:42:05 +0200 |
| commit | b24f73775983eb7a30d50f608ccc8702e54c57c3 (patch) | |
| tree | 1ac774a5810f821740f6c721e348a34b8c9408ac /tests/sva/basic01.sv | |
| parent | 90d8329f642e710e8d4ce358cfb9543b85bcd822 (diff) | |
| download | yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.tar.gz yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.tar.bz2 yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.zip | |
Improve SVA tests, add Makefile and scripts
Diffstat (limited to 'tests/sva/basic01.sv')
| -rw-r--r-- | tests/sva/basic01.sv | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/sva/basic01.sv b/tests/sva/basic01.sv index 596e48db0..74ab93430 100644 --- a/tests/sva/basic01.sv +++ b/tests/sva/basic01.sv @@ -8,5 +8,9 @@ module top (input logic clock, ctrl); end a_rw: assert property ( @(posedge clock) !(read && write) ); +`ifdef FAIL a_wr: assert property ( @(posedge clock) write |-> ready ); +`else + a_wr: assert property ( @(posedge clock) write |=> ready ); +`endif endmodule |