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author | Eddie Hung <eddie@fpgeh.com> | 2020-01-23 19:55:11 -0800 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-23 19:55:11 -0800 |
commit | dca1c806eca0219fb609acfd111fbf9073c6908f (patch) | |
tree | 785b2647c1e53dee0af1687cf03160aee7e04bdf /tests/simple_abc9/abc9.v | |
parent | 245873d42d7975b6c303c2d04b75f3cafc6c5697 (diff) | |
download | yosys-dca1c806eca0219fb609acfd111fbf9073c6908f.tar.gz yosys-dca1c806eca0219fb609acfd111fbf9073c6908f.tar.bz2 yosys-dca1c806eca0219fb609acfd111fbf9073c6908f.zip |
simple_abc9 tests to discard whitebox before write for sim
Diffstat (limited to 'tests/simple_abc9/abc9.v')
-rw-r--r-- | tests/simple_abc9/abc9.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 52ccb3e1d..e5837d480 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -213,7 +213,7 @@ module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encode input rst; endmodule -(* abc9_box_id=1 *) +(* abc9_box_id=1, whitebox *) module MUXF8(input I0, I1, S, output O); endmodule |