Merge branch 'master' into clk2ff-better-names

48 files changed, 674 insertions, 57 deletions

diff --git a/tests/simple/asgn_binop.sv b/tests/simple/asgn_binop.sv
new file mode 100644
index 000000000..b134e5697
--- /dev/null
+++ b/tests/simple/asgn_binop.sv
@@ -0,0 +1,23 @@
+`define TEST(name, asgnop)\
+	module test_``name ( \
+		input logic [3:0] a, b, \
+		output logic [3:0] c \
+	); \
+		always @* begin \
+			c = a; \
+			c asgnop b; \
+		end \
+	endmodule
+
+`TEST(add, +=)
+`TEST(sub, -=)
+`TEST(mul, *=)
+`TEST(div, /=)
+`TEST(mod, %=)
+`TEST(bit_and, &=)
+`TEST(bit_or , |=)
+`TEST(bit_xor, ^=)
+`TEST(shl, <<=)
+`TEST(shr, >>=)
+`TEST(sshl, <<<=)
+`TEST(sshr, >>>=)
diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
index adef34f5b..d6e36fb80 100644
--- a/tests/simple/attrib01_module.v
+++ b/tests/simple/attrib01_module.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib01_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,12 +10,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib01_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib01_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib02_port_decl.v b/tests/simple/attrib02_port_decl.v
index 3505e7265..989213b77 100644
--- a/tests/simple/attrib02_port_decl.v
+++ b/tests/simple/attrib02_port_decl.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib02_bar(clk, rst, inp, out);
   (* this_is_clock = 1 *)
   input  wire clk;
   (* this_is_reset = 1 *)
@@ -13,13 +13,13 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib02_foo(clk, rst, inp, out);
   (* this_is_the_master_clock *)
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib02_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib03_parameter.v b/tests/simple/attrib03_parameter.v
index 562d225cd..d2ae98978 100644
--- a/tests/simple/attrib03_parameter.v
+++ b/tests/simple/attrib03_parameter.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib03_bar(clk, rst, inp, out);
 
   (* bus_width *)
   parameter WIDTH = 2;
@@ -17,12 +17,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib03_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp;
   output wire [7:0] out;
 
-  bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
+  attrib03_bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib04_net_var.v b/tests/simple/attrib04_net_var.v
index 8b5523406..98826e971 100644
--- a/tests/simple/attrib04_net_var.v
+++ b/tests/simple/attrib04_net_var.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib04_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -21,12 +21,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib04_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib04_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib05_port_conn.v.DISABLED b/tests/simple/attrib05_port_conn.v.DISABLED
index e20e66319..8cc471f4e 100644
--- a/tests/simple/attrib05_port_conn.v.DISABLED
+++ b/tests/simple/attrib05_port_conn.v.DISABLED
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib05_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,12 +10,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib05_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
-  bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
+  attrib05_bar bar_instance ( (* clock_connected *) clk, rst, (* this_is_the_input *) inp, out);
 endmodule
 
diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v
index e21173c58..2bc136f9a 100644
--- a/tests/simple/attrib06_operator_suffix.v
+++ b/tests/simple/attrib06_operator_suffix.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp_a, inp_b, out);
+module attrib06_bar(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
@@ -11,13 +11,13 @@ module bar(clk, rst, inp_a, inp_b, out);
 
 endmodule
 
-module foo(clk, rst, inp_a, inp_b, out);
+module attrib06_foo(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
   input  wire [7:0] inp_b;
   output wire [7:0] out;
 
-  bar bar_instance (clk, rst, inp_a, inp_b, out);
+  attrib06_bar bar_instance (clk, rst, inp_a, inp_b, out);
 endmodule
 
diff --git a/tests/simple/attrib07_func_call.v.DISABLED b/tests/simple/attrib07_func_call.v.DISABLED
index f55ef2316..282fc5da7 100644
--- a/tests/simple/attrib07_func_call.v.DISABLED
+++ b/tests/simple/attrib07_func_call.v.DISABLED
@@ -1,4 +1,4 @@
-function [7:0] do_add;
+function [7:0] attrib07_do_add;
   input [7:0] inp_a;
   input [7:0] inp_b;
 
@@ -6,7 +6,7 @@ function [7:0] do_add;
 
 endfunction
 
-module foo(clk, rst, inp_a, inp_b, out);
+module attri07_foo(clk, rst, inp_a, inp_b, out);
   input  wire clk;
   input  wire rst;
   input  wire [7:0] inp_a;
@@ -15,7 +15,7 @@ module foo(clk, rst, inp_a, inp_b, out);
 
   always @(posedge clk)
     if (rst) out <= 0;
-    else     out <= do_add (* combinational_adder *) (inp_a, inp_b);
+    else     out <= attrib07_do_add (* combinational_adder *) (inp_a, inp_b);
 
 endmodule
 
diff --git a/tests/simple/attrib08_mod_inst.v b/tests/simple/attrib08_mod_inst.v
index c5a32234e..759e67c7b 100644
--- a/tests/simple/attrib08_mod_inst.v
+++ b/tests/simple/attrib08_mod_inst.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib08_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
@@ -10,13 +10,13 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib08_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire inp;
   output wire out;
 
   (* my_module_instance = 99 *)
-  bar bar_instance (clk, rst, inp, out);
+  attrib08_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/attrib09_case.v b/tests/simple/attrib09_case.v
index 8551bf9d0..a72b81dda 100644
--- a/tests/simple/attrib09_case.v
+++ b/tests/simple/attrib09_case.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib09_bar(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [1:0] inp;
@@ -15,12 +15,12 @@ module bar(clk, rst, inp, out);
 
 endmodule
 
-module foo(clk, rst, inp, out);
+module attrib09_foo(clk, rst, inp, out);
   input  wire clk;
   input  wire rst;
   input  wire [1:0] inp;
   output wire [1:0] out;
 
-  bar bar_instance (clk, rst, inp, out);
+  attrib09_bar bar_instance (clk, rst, inp, out);
 endmodule
 
diff --git a/tests/simple/case_expr_const.v b/tests/simple/case_expr_const.v
new file mode 100644
index 000000000..d9169c084
--- /dev/null
+++ b/tests/simple/case_expr_const.v
@@ -0,0 +1,49 @@
+// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
+// the constant and non-constant case evaluation logic is covered
+module case_expr_const_top(
+	// expected to output all 1s
+    output reg a, b, c, d, e, f, g, h
+);
+    initial begin
+        case (2'b0)
+            1'b0:    a = 1;
+            default: a = 0;
+        endcase
+        case (2'sb11)
+            2'sb01:  b = 0;
+            1'sb1:   b = 1;
+        endcase
+        case (2'sb11)
+            1'sb0:   c = 0;
+            1'sb1:   c = 1;
+        endcase
+        case (2'sb11)
+            1'b0:    d = 0;
+            1'sb1:   d = 0;
+            default: d = 1;
+        endcase
+        case (2'b11)
+            1'sb0:   e = 0;
+            1'sb1:   e = 0;
+            default: e = 1;
+        endcase
+        case (1'sb1)
+            1'sb0:   f = 0;
+            2'sb11:  f = 1;
+            default: f = 0;
+        endcase
+        case (1'sb1)
+            1'sb0:   g = 0;
+            3'b0:    g = 0;
+            2'sb11:  g = 0;
+            default: g = 1;
+        endcase
+        case (1'sb1)
+            1'sb0:   h = 0;
+            1'b1:    h = 1;
+            3'b0:    h = 0;
+            2'sb11:  h = 0;
+            default: h = 0;
+        endcase
+    end
+endmodule
diff --git a/tests/simple/case_expr_extend.sv b/tests/simple/case_expr_extend.sv
new file mode 100644
index 000000000..d4ca2aa9b
--- /dev/null
+++ b/tests/simple/case_expr_extend.sv
@@ -0,0 +1,11 @@
+module top(
+    output logic [5:0] out
+);
+initial begin
+    out = '0;
+    case (1'b1 << 1)
+        2'b10: out = '1;
+        default: out = '0;
+    endcase
+end
+endmodule
diff --git a/tests/simple/case_expr_non_const.v b/tests/simple/case_expr_non_const.v
new file mode 100644
index 000000000..6dfc2e54e
--- /dev/null
+++ b/tests/simple/case_expr_non_const.v
@@ -0,0 +1,59 @@
+// Note: case_expr_{,non_}const.v should be modified in tandem to ensure both
+// the constant and non-constant case evaluation logic is covered
+module case_expr_non_const_top(
+	// expected to output all 1s
+    output reg a, b, c, d, e, f, g, h
+);
+    reg x_1b0 = 1'b0;
+    reg x_1b1 = 1'b1;
+    reg signed x_1sb0 = 1'sb0;
+    reg signed x_1sb1 = 1'sb1;
+    reg [1:0] x_2b0 = 2'b0;
+    reg [1:0] x_2b11 = 2'b11;
+    reg signed [1:0] x_2sb01 = 2'sb01;
+    reg signed [1:0] x_2sb11 = 2'sb11;
+    reg [2:0] x_3b0 = 3'b0;
+
+    initial begin
+        case (x_2b0)
+            x_1b0:   a = 1;
+            default: a = 0;
+        endcase
+        case (x_2sb11)
+            x_2sb01: b = 0;
+            x_1sb1:  b = 1;
+        endcase
+        case (x_2sb11)
+            x_1sb0:  c = 0;
+            x_1sb1:  c = 1;
+        endcase
+        case (x_2sb11)
+            x_1b0:   d = 0;
+            x_1sb1:  d = 0;
+            default: d = 1;
+        endcase
+        case (x_2b11)
+            x_1sb0:  e = 0;
+            x_1sb1:  e = 0;
+            default: e = 1;
+        endcase
+        case (x_1sb1)
+            x_1sb0:  f = 0;
+            x_2sb11: f = 1;
+            default: f = 0;
+        endcase
+        case (x_1sb1)
+            x_1sb0:  g = 0;
+            x_3b0:   g = 0;
+            x_2sb11: g = 0;
+            default: g = 1;
+        endcase
+        case (x_1sb1)
+            x_1sb0:  h = 0;
+            x_1b1:   h = 1;
+            x_3b0:   h = 0;
+            x_2sb11: h = 0;
+            default: h = 0;
+        endcase
+    end
+endmodule
diff --git a/tests/simple/case_expr_query.sv b/tests/simple/case_expr_query.sv
new file mode 100644
index 000000000..844dfb713
--- /dev/null
+++ b/tests/simple/case_expr_query.sv
@@ -0,0 +1,32 @@
+module top(
+    output logic [5:0] out
+);
+initial begin
+    out = '0;
+    case ($bits (out)) 6:
+    case ($size (out)) 6:
+    case ($high (out)) 5:
+    case ($low  (out)) 0:
+    case ($left (out)) 5:
+    case ($right(out)) 0:
+    case (6) $bits (out):
+    case (6) $size (out):
+    case (5) $high (out):
+    case (0) $low  (out):
+    case (5) $left (out):
+    case (0) $right(out):
+        out = '1;
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+    endcase
+end
+endmodule
diff --git a/tests/simple/case_large.v b/tests/simple/case_large.v
new file mode 100644
index 000000000..ec8ed6038
--- /dev/null
+++ b/tests/simple/case_large.v
@@ -0,0 +1,273 @@
+module case_lage_top (
+    input wire [127:0] x,
+    output reg [31:0] y
+);
+    localparam A = 32'hDEAD_BEEF;
+    localparam B = 32'h0BAD_0B01;
+    localparam C = 32'hC001_D00D;
+    localparam D = 32'h1234_5678;
+
+    always @*
+        case (x)
+
+            {C,A,D,B}: y = 142;
+            {C,A,D,A}: y = 141;
+            {D,D,A,A}: y = 241;
+            {A,C,C,D}: y = 44;
+            {A,A,A,C}: y = 3;
+            {A,B,A,C}: y = 19;
+            {A,D,C,C}: y = 59;
+            {A,A,C,C}: y = 11;
+            {D,C,B,B}: y = 230;
+            {A,A,D,D}: y = 16;
+            {A,C,A,A}: y = 33;
+            {A,D,D,D}: y = 64;
+            {D,B,C,B}: y = 218;
+            {A,C,B,D}: y = 40;
+            {C,A,B,B}: y = 134;
+            {A,C,C,C}: y = 43;
+            {D,A,D,D}: y = 208;
+            {A,B,C,A}: y = 25;
+            {B,A,B,B}: y = 70;
+            {A,C,B,B}: y = 38;
+            {C,C,C,B}: y = 170;
+            {C,D,A,C}: y = 179;
+            {B,C,D,B}: y = 110;
+            {A,D,A,C}: y = 51;
+            {C,C,B,B}: y = 166;
+            {D,D,D,B}: y = 254;
+            {C,A,D,C}: y = 143;
+            {C,D,D,B}: y = 190;
+            {C,B,A,A}: y = 145;
+            {C,B,A,C}: y = 147;
+            {B,C,C,B}: y = 106;
+            {C,D,C,A}: y = 185;
+            {C,D,B,D}: y = 184;
+            {D,D,D,D}: y = 256;
+            {D,C,C,C}: y = 235;
+            {D,C,D,B}: y = 238;
+            {A,B,D,C}: y = 31;
+            {A,C,A,D}: y = 36;
+            {C,B,C,B}: y = 154;
+            {A,B,A,A}: y = 17;
+            {C,B,B,A}: y = 149;
+            {B,B,D,C}: y = 95;
+            {B,D,C,B}: y = 122;
+            {D,B,A,A}: y = 209;
+            {B,A,B,A}: y = 69;
+            {B,A,D,A}: y = 77;
+            {A,B,B,B}: y = 22;
+            {C,C,C,C}: y = 171;
+            {C,A,C,B}: y = 138;
+            {B,A,D,D}: y = 80;
+            {C,D,D,C}: y = 191;
+            {B,A,A,C}: y = 67;
+            {D,C,D,C}: y = 239;
+            {C,D,D,D}: y = 192;
+            {C,D,B,B}: y = 182;
+            {B,B,A,C}: y = 83;
+            {D,A,A,D}: y = 196;
+            {A,C,C,B}: y = 42;
+            {B,C,A,A}: y = 97;
+            {A,D,B,A}: y = 53;
+            {D,D,B,C}: y = 247;
+            {A,A,C,A}: y = 9;
+            {D,A,C,B}: y = 202;
+            {A,C,B,C}: y = 39;
+            {B,C,B,A}: y = 101;
+            {B,B,B,C}: y = 87;
+            {C,B,A,B}: y = 146;
+            {B,D,A,D}: y = 116;
+            {A,B,D,D}: y = 32;
+            {B,A,B,C}: y = 71;
+            {C,A,A,A}: y = 129;
+            {B,A,D,C}: y = 79;
+            {B,A,C,B}: y = 74;
+            {B,B,D,B}: y = 94;
+            {B,B,C,C}: y = 91;
+            {D,C,C,A}: y = 233;
+            {C,A,B,A}: y = 133;
+            {D,A,B,A}: y = 197;
+            {D,B,B,D}: y = 216;
+            {C,C,A,C}: y = 163;
+            {D,D,B,A}: y = 245;
+            {B,A,D,B}: y = 78;
+            {A,B,C,D}: y = 28;
+            {C,C,C,D}: y = 172;
+            {D,C,A,D}: y = 228;
+            {A,C,D,A}: y = 45;
+            {B,D,C,C}: y = 123;
+            {C,B,A,D}: y = 148;
+            {B,D,B,B}: y = 118;
+            {A,D,A,B}: y = 50;
+            {C,B,B,C}: y = 151;
+            {A,A,A,A}: y = 1;
+            {A,A,B,B}: y = 6;
+            {B,B,B,B}: y = 86;
+            {A,D,A,A}: y = 49;
+            {A,A,A,B}: y = 2;
+            {B,D,D,A}: y = 125;
+            {C,C,D,B}: y = 174;
+            {D,A,D,B}: y = 206;
+            {D,D,B,D}: y = 248;
+            {A,A,A,D}: y = 4;
+            {B,A,A,B}: y = 66;
+            {B,C,C,A}: y = 105;
+            {B,C,C,C}: y = 107;
+            {D,D,D,C}: y = 255;
+            {B,C,D,D}: y = 112;
+            {A,D,B,C}: y = 55;
+            {C,C,C,A}: y = 169;
+            {C,D,B,C}: y = 183;
+            {A,A,B,D}: y = 8;
+            {D,C,B,A}: y = 229;
+            {C,B,D,A}: y = 157;
+            {A,D,D,C}: y = 63;
+            {D,A,D,A}: y = 205;
+            {A,A,B,C}: y = 7;
+            {A,C,A,B}: y = 34;
+            {C,B,D,C}: y = 159;
+            {C,C,D,D}: y = 176;
+            {D,D,D,A}: y = 253;
+            {A,B,B,D}: y = 24;
+            {B,B,C,A}: y = 89;
+            {B,D,C,A}: y = 121;
+            {A,B,C,C}: y = 27;
+            {A,A,D,C}: y = 15;
+            {A,B,B,A}: y = 21;
+            {A,D,A,D}: y = 52;
+            {D,D,C,C}: y = 251;
+            {C,D,A,B}: y = 178;
+            {A,A,D,B}: y = 14;
+            {D,B,D,B}: y = 222;
+            {A,C,C,A}: y = 41;
+            {D,D,A,C}: y = 243;
+            {A,C,D,B}: y = 46;
+            {B,B,B,D}: y = 88;
+            {D,B,B,B}: y = 214;
+            {C,C,B,D}: y = 168;
+            {A,D,D,A}: y = 61;
+            {D,A,C,C}: y = 203;
+            {D,C,A,C}: y = 227;
+            {C,D,C,D}: y = 188;
+            {D,B,D,D}: y = 224;
+            {A,C,D,C}: y = 47;
+            {B,A,B,D}: y = 72;
+            {A,B,B,C}: y = 23;
+            {C,C,D,A}: y = 173;
+            {D,B,C,C}: y = 219;
+            {D,B,C,A}: y = 217;
+            {A,D,C,D}: y = 60;
+            {B,B,D,A}: y = 93;
+            {A,D,C,A}: y = 57;
+            {C,C,A,A}: y = 161;
+            {C,B,B,D}: y = 152;
+            {B,B,B,A}: y = 85;
+            {B,D,A,A}: y = 113;
+            {D,C,D,A}: y = 237;
+            {B,C,B,C}: y = 103;
+            {A,B,C,B}: y = 26;
+            {C,D,A,D}: y = 180;
+            {A,D,B,D}: y = 56;
+            {D,C,A,B}: y = 226;
+            {D,B,B,C}: y = 215;
+            {D,A,B,C}: y = 199;
+            {B,D,A,C}: y = 115;
+            {C,B,C,D}: y = 156;
+            {B,D,D,B}: y = 126;
+            {D,D,C,B}: y = 250;
+            {D,C,C,D}: y = 236;
+            {B,C,B,D}: y = 104;
+            {C,B,C,A}: y = 153;
+            {C,B,B,B}: y = 150;
+            {C,D,C,B}: y = 186;
+            {C,D,C,C}: y = 187;
+            {A,D,B,B}: y = 54;
+            {D,C,C,B}: y = 234;
+            {C,B,D,D}: y = 160;
+            {A,B,A,D}: y = 20;
+            {C,C,B,A}: y = 165;
+            {C,D,D,A}: y = 189;
+            {C,C,D,C}: y = 175;
+            {D,B,D,C}: y = 223;
+            {B,C,A,B}: y = 98;
+            {C,C,A,B}: y = 162;
+            {B,C,D,A}: y = 109;
+            {D,A,B,D}: y = 200;
+            {B,D,C,D}: y = 124;
+            {D,D,C,A}: y = 249;
+            {B,A,C,C}: y = 75;
+            {A,A,C,B}: y = 10;
+            {C,A,B,D}: y = 136;
+            {B,B,C,D}: y = 92;
+            {D,D,C,D}: y = 252;
+            {B,C,A,D}: y = 100;
+            {C,A,C,C}: y = 139;
+            {C,A,C,D}: y = 140;
+            {D,C,A,A}: y = 225;
+            {A,D,C,B}: y = 58;
+            {D,B,C,D}: y = 220;
+            {D,C,B,D}: y = 232;
+            {B,A,C,D}: y = 76;
+            {B,B,D,D}: y = 96;
+            {D,D,B,B}: y = 246;
+            {C,D,A,A}: y = 177;
+            {D,D,A,B}: y = 242;
+            {A,A,D,A}: y = 13;
+            {B,B,A,D}: y = 84;
+            {B,C,D,C}: y = 111;
+            {D,A,A,B}: y = 194;
+            {C,A,B,C}: y = 135;
+            {D,A,A,C}: y = 195;
+            {B,B,A,B}: y = 82;
+            {D,C,D,D}: y = 240;
+            {B,C,C,D}: y = 108;
+            {D,B,A,C}: y = 211;
+            {A,C,D,D}: y = 48;
+            {D,A,A,A}: y = 193;
+            {C,A,A,B}: y = 130;
+            {D,B,A,D}: y = 212;
+            {D,A,B,B}: y = 198;
+            {A,C,B,A}: y = 37;
+            {B,D,B,D}: y = 120;
+            {C,C,B,C}: y = 167;
+            {D,B,A,B}: y = 210;
+            {A,B,A,B}: y = 18;
+            {B,C,B,B}: y = 102;
+            {B,B,A,A}: y = 81;
+            {D,D,A,D}: y = 244;
+            {A,B,D,B}: y = 30;
+            {A,C,A,C}: y = 35;
+            {A,A,C,D}: y = 12;
+            {B,D,B,C}: y = 119;
+            {B,C,A,C}: y = 99;
+            {D,A,C,A}: y = 201;
+            {B,A,A,D}: y = 68;
+            {C,A,A,D}: y = 132;
+            {B,A,C,A}: y = 73;
+            {C,C,A,D}: y = 164;
+            {B,D,B,A}: y = 117;
+            {A,D,D,B}: y = 62;
+            {B,D,D,C}: y = 127;
+            {A,B,D,A}: y = 29;
+            {C,D,B,A}: y = 181;
+            {B,B,C,B}: y = 90;
+            {B,D,A,B}: y = 114;
+            {B,D,D,D}: y = 128;
+            {C,A,C,A}: y = 137;
+            {A,A,B,A}: y = 5;
+            {C,A,D,D}: y = 144;
+            {D,C,B,C}: y = 231;
+            {D,A,C,D}: y = 204;
+            {C,A,A,C}: y = 131;
+            {C,B,D,B}: y = 158;
+            {B,A,A,A}: y = 65;
+            {D,A,D,C}: y = 207;
+            {D,B,B,A}: y = 213;
+            {D,B,D,A}: y = 221;
+            {C,B,C,C}: y = 155;
+
+            default: y = 0;
+
+        endcase
+endmodule
diff --git a/tests/simple/const_branch_finish.v b/tests/simple/const_branch_finish.v
index f585be87a..7e365eeb4 100644
--- a/tests/simple/const_branch_finish.v
+++ b/tests/simple/const_branch_finish.v
@@ -4,7 +4,7 @@
 		$finish; \
 	end
 
-module top;
+module case_branch_finish_top;
 	parameter WIDTH = 32;
 	integer j;
 	initial begin
diff --git a/tests/simple/const_fold_func.v b/tests/simple/const_fold_func.v
index ee2f12e06..b3f476ce3 100644
--- a/tests/simple/const_fold_func.v
+++ b/tests/simple/const_fold_func.v
@@ -1,4 +1,4 @@
-module top(
+module const_fold_func_top(
 	input wire [3:0] inp,
 	output wire [3:0] out1, out2, out3, out4, out5,
 	output reg [3:0] out6
diff --git a/tests/simple/const_func_shadow.v b/tests/simple/const_func_shadow.v
index ca63606d9..fb4f148f6 100644
--- a/tests/simple/const_func_shadow.v
+++ b/tests/simple/const_func_shadow.v
@@ -1,4 +1,4 @@
-module top(w, x, y, z);
+module const_func_shadow_top(w, x, y, z);
 	function [11:0] func;
 		input reg [2:0] x;
 		input reg [2:0] y;
diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv
index b0a087ecb..77d7ba26b 100644
--- a/tests/simple/defvalue.sv
+++ b/tests/simple/defvalue.sv
@@ -1,4 +1,4 @@
-module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
+module defvalue_top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
 	cnt #(1) foo (.clock, .cnt(cnt1), .delta);
 	cnt #(2) bar (.clock, .cnt(cnt2));
 endmodule
diff --git a/tests/simple/func_block.v b/tests/simple/func_block.v
index be759d1a9..0ac7ca3bf 100644
--- a/tests/simple/func_block.v
+++ b/tests/simple/func_block.v
@@ -1,6 +1,6 @@
 `default_nettype none
 
-module top(inp, out1, out2, out3);
+module func_block_top(inp, out1, out2, out3);
 	input wire [31:0] inp;
 
 	function automatic [31:0] func1;
diff --git a/tests/simple/func_recurse.v b/tests/simple/func_recurse.v
index d61c8cc06..02cfbcddf 100644
--- a/tests/simple/func_recurse.v
+++ b/tests/simple/func_recurse.v
@@ -1,4 +1,4 @@
-module top(
+module func_recurse_top(
 	input wire [3:0] inp,
 	output wire [3:0] out1, out2
 );
diff --git a/tests/simple/func_width_scope.v b/tests/simple/func_width_scope.v
index ce81e894e..2f82988ae 100644
--- a/tests/simple/func_width_scope.v
+++ b/tests/simple/func_width_scope.v
@@ -1,4 +1,4 @@
-module top(inp, out1, out2);
+module func_width_scope_top(inp, out1, out2);
 	input wire signed inp;
 
 	localparam WIDTH_A = 5;
diff --git a/tests/simple/genblk_collide.v b/tests/simple/genblk_collide.v
index f42dd2cfc..118c0b008 100644
--- a/tests/simple/genblk_collide.v
+++ b/tests/simple/genblk_collide.v
@@ -1,6 +1,6 @@
 `default_nettype none
 
-module top1;
+module genblock_collide_top1;
 	generate
 		if (1) begin : foo
 			if (1) begin : bar
@@ -12,7 +12,7 @@ module top1;
 	endgenerate
 endmodule
 
-module top2;
+module genblock_collide_top2;
 	genvar i;
 	generate
 		if (1) begin : foo
diff --git a/tests/simple/genblk_dive.v b/tests/simple/genblk_dive.v
index 98d0e1f4b..ca0c0d4a1 100644
--- a/tests/simple/genblk_dive.v
+++ b/tests/simple/genblk_dive.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top(output wire x);
+module genblk_dive_top(output wire x);
 	generate
 		if (1) begin : Z
 			if (1) begin : A
diff --git a/tests/simple/genblk_order.v b/tests/simple/genblk_order.v
index 7c3a7a756..c80c1ac1a 100644
--- a/tests/simple/genblk_order.v
+++ b/tests/simple/genblk_order.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top(
+module genblk_order_top(
 	output wire out1,
 	output wire out2
 );
diff --git a/tests/simple/genblk_port_shadow.v b/tests/simple/genblk_port_shadow.v
index a04631a20..c1348632c 100644
--- a/tests/simple/genblk_port_shadow.v
+++ b/tests/simple/genblk_port_shadow.v
@@ -1,4 +1,4 @@
-module top(x);
+module genblock_port_shadow_top(x);
 	generate
 		if (1) begin : blk
 			wire x;
diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v
index 123afaeab..b03044fde 100644
--- a/tests/simple/hierarchy.v
+++ b/tests/simple/hierarchy.v
@@ -1,6 +1,6 @@
 
 (* top *)
-module top(a, b, y1, y2, y3, y4);
+module hierarchy_top(a, b, y1, y2, y3, y4);
 input [3:0] a;
 input signed [3:0] b;
 output [7:0] y1, y2, y3, y4;
diff --git a/tests/simple/ifdef_1.v b/tests/simple/ifdef_1.v
index fa962355c..f1358185c 100644
--- a/tests/simple/ifdef_1.v
+++ b/tests/simple/ifdef_1.v
@@ -1,4 +1,4 @@
-module top(o1, o2, o3, o4);
+module ifdef_1_top(o1, o2, o3, o4);
 
 `define FAIL input wire not_a_port;
 
diff --git a/tests/simple/ifdef_2.v b/tests/simple/ifdef_2.v
index 6dd89efed..9fae7570d 100644
--- a/tests/simple/ifdef_2.v
+++ b/tests/simple/ifdef_2.v
@@ -1,4 +1,4 @@
-module top(o1, o2, o3);
+module ifdef_2_top(o1, o2, o3);
 
 output wire o1;
 
diff --git a/tests/simple/lesser_size_cast.sv b/tests/simple/lesser_size_cast.sv
new file mode 100644
index 000000000..8c0bc9814
--- /dev/null
+++ b/tests/simple/lesser_size_cast.sv
@@ -0,0 +1,7 @@
+module top (
+    input signed [1:0] a,
+    input signed [2:0] b,
+    output signed [4:0] c
+);
+    assign c = 2'(a) * b;
+endmodule
diff --git a/tests/simple/local_loop_var.sv b/tests/simple/local_loop_var.sv
index 46b4e5c22..42860e218 100644
--- a/tests/simple/local_loop_var.sv
+++ b/tests/simple/local_loop_var.sv
@@ -1,4 +1,4 @@
-module top(out);
+module local_loop_top(out);
 	output integer out;
 	initial begin
 		integer i;
diff --git a/tests/simple/loop_prefix_case.v b/tests/simple/loop_prefix_case.v
new file mode 100644
index 000000000..0cfa00547
--- /dev/null
+++ b/tests/simple/loop_prefix_case.v
@@ -0,0 +1,18 @@
+module loop_prefix_case_top(
+	input wire x,
+	output reg y
+);
+	localparam I = 1;
+	genvar i;
+	generate
+		for (i = 0; i < 1; i = i + 1) begin : blk
+			wire [i:i] z = x;
+		end
+	endgenerate
+	always @* begin
+		case (blk[I - 1].z)
+			1: y = 0;
+			0: y = 1;
+		endcase
+	end
+endmodule
diff --git a/tests/simple/loop_var_shadow.v b/tests/simple/loop_var_shadow.v
index 0222a4493..b75a15ab0 100644
--- a/tests/simple/loop_var_shadow.v
+++ b/tests/simple/loop_var_shadow.v
@@ -1,4 +1,4 @@
-module top(out);
+module loop_var_shadow_top(out);
 	genvar i;
 	generate
 		for (i = 0; i < 2; i = i + 1) begin : loop
diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv
index 75c4cd136..5fc9e2881 100644
--- a/tests/simple/macro_arg_spaces.sv
+++ b/tests/simple/macro_arg_spaces.sv
@@ -1,4 +1,4 @@
-module top(
+module macro_arg_spaces_top(
 	input wire [31:0] i,
 	output wire [31:0] x, y, z
 );
diff --git a/tests/simple/macro_arg_surrounding_spaces.v b/tests/simple/macro_arg_surrounding_spaces.v
index 3dbb5ea01..e0239c08b 100644
--- a/tests/simple/macro_arg_surrounding_spaces.v
+++ b/tests/simple/macro_arg_surrounding_spaces.v
@@ -1,4 +1,4 @@
-module top(
+module macr_arg_surrounding_spaces_top(
 	IDENT_V_,
 	IDENT_W_,
 	IDENT_X_,
diff --git a/tests/simple/matching_end_labels.sv b/tests/simple/matching_end_labels.sv
new file mode 100644
index 000000000..2d42e7e10
--- /dev/null
+++ b/tests/simple/matching_end_labels.sv
@@ -0,0 +1,29 @@
+module matching_end_labels_top(
+    output reg [7:0]
+    out1, out2, out3, out4
+);
+    initial begin
+        begin : blk1
+            reg x;
+            x = 1;
+        end
+        out1 = blk1.x;
+        begin : blk2
+            reg x;
+            x = 2;
+        end : blk2
+        out2 = blk2.x;
+    end
+    if (1) begin
+        if (1) begin : blk3
+            reg x;
+            assign x = 3;
+        end
+        assign out3 = blk3.x;
+        if (1) begin : blk4
+            reg x;
+            assign x = 4;
+        end : blk4
+        assign out4 = blk4.x;
+    end
+endmodule
diff --git a/tests/simple/mem2reg_bounds_tern.v b/tests/simple/mem2reg_bounds_tern.v
new file mode 100644
index 000000000..0e6852fe7
--- /dev/null
+++ b/tests/simple/mem2reg_bounds_tern.v
@@ -0,0 +1,19 @@
+module mem2reg_bounds_term_top(
+    input clk,
+    input wire [1:0] sel,
+    input wire [7:0] base,
+    output reg [7:0] line
+);
+    reg [0:7] mem [0:2];
+
+    generate
+        genvar i;
+        for (i = 0; i < 4; i = i + 1) begin : gen
+            always @(posedge clk)
+                mem[i] <= i == 0 ? base : mem[i - 1] + 1;
+        end
+    endgenerate
+
+    always @(posedge clk)
+        line = mem[sel];
+endmodule
diff --git a/tests/simple/memwr_port_connection.sv b/tests/simple/memwr_port_connection.sv
new file mode 100644
index 000000000..5bf414e08
--- /dev/null
+++ b/tests/simple/memwr_port_connection.sv
@@ -0,0 +1,13 @@
+module producer(
+    output logic [3:0] out
+);
+    assign out = 4'hA;
+endmodule
+
+module top(
+    output logic [3:0] out
+);
+    logic [3:0] v[0:0];
+    producer p(v[0]);
+    assign out = v[0];
+endmodule
diff --git a/tests/simple/module_scope.v b/tests/simple/module_scope.v
new file mode 100644
index 000000000..d07783912
--- /dev/null
+++ b/tests/simple/module_scope.v
@@ -0,0 +1,29 @@
+`default_nettype none
+
+module module_scope_Example(o1, o2);
+   parameter [31:0] v1 = 10;
+   parameter [31:0] v2 = 20;
+   output [31:0] o1, o2;
+   assign module_scope_Example.o1 = module_scope_Example.v1;
+   assign module_scope_Example.o2 = module_scope_Example.v2;
+endmodule
+
+module module_scope_ExampleLong(o1, o2);
+   parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1 = 10;
+   parameter [31:0] ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2 = 20;
+   output [31:0] o1, o2;
+   assign module_scope_ExampleLong.o1 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum1;
+   assign module_scope_ExampleLong.o2 = module_scope_ExampleLong.ThisIsAnExtremelyLongParameterNameToTriggerTheSHA1Checksum2;
+endmodule
+
+module module_scope_top(
+   output [31:0] a1, a2, b1, b2, c1, c2,
+   output [31:0] d1, d2, e1, e2, f1, f2
+);
+   module_scope_Example a(a1, a2);
+   module_scope_Example #(1) b(b1, b2);
+   module_scope_Example #(1, 2) c(c1, c2);
+   module_scope_ExampleLong d(d1, d2);
+   module_scope_ExampleLong #(1) e(e1, e2);
+   module_scope_ExampleLong #(1, 2) f(f1, f2);
+endmodule
diff --git a/tests/simple/module_scope_case.v b/tests/simple/module_scope_case.v
new file mode 100644
index 000000000..bceba4424
--- /dev/null
+++ b/tests/simple/module_scope_case.v
@@ -0,0 +1,11 @@
+module module_scope_case_top(
+	input wire x,
+	output reg y
+);
+	always @* begin
+		case (module_scope_case_top.x)
+			1: module_scope_case_top.y = 0;
+			0: module_scope_case_top.y = 1;
+		endcase
+	end
+endmodule
diff --git a/tests/simple/named_genblk.v b/tests/simple/named_genblk.v
index b8300fc4d..b98b7c8ce 100644
--- a/tests/simple/named_genblk.v
+++ b/tests/simple/named_genblk.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top;
+module named_genblk_top;
 	generate
 		if (1) begin
 			wire t;
diff --git a/tests/simple/nested_genblk_resolve.v b/tests/simple/nested_genblk_resolve.v
index da5593f8a..70bbc611b 100644
--- a/tests/simple/nested_genblk_resolve.v
+++ b/tests/simple/nested_genblk_resolve.v
@@ -1,5 +1,5 @@
 `default_nettype none
-module top;
+module nested_genblk_resolve_top;
     generate
         if (1) begin
             wire x;
diff --git a/tests/simple/signed_full_slice.v b/tests/simple/signed_full_slice.v
new file mode 100644
index 000000000..f8a331578
--- /dev/null
+++ b/tests/simple/signed_full_slice.v
@@ -0,0 +1,29 @@
+module pass_through_a(
+    input wire [31:0] inp,
+    output wire [31:0] out
+);
+    assign out[31:0] = inp[31:0];
+endmodule
+
+module top_a(
+    input wire signed [31:0] inp,
+    output wire signed [31:0] out
+);
+    pass_through_a pt(inp[31:0], out[31:0]);
+endmodule
+
+// tests both module declaration orderings
+
+module top_b(
+    input wire signed [31:0] inp,
+    output wire signed [31:0] out
+);
+    pass_through_b pt(inp[31:0], out[31:0]);
+endmodule
+
+module pass_through_b(
+    input wire [31:0] inp,
+    output wire [31:0] out
+);
+    assign out[31:0] = inp[31:0];
+endmodule
diff --git a/tests/simple/string_format.v b/tests/simple/string_format.v
index ce45ca1e9..cb7b419ac 100644
--- a/tests/simple/string_format.v
+++ b/tests/simple/string_format.v
@@ -1,4 +1,4 @@
-module top;
+module string_format_top;
 	parameter STR = "something interesting";
 	initial begin
 		$display("A: %s", STR);
diff --git a/tests/simple/unnamed_block_decl.sv b/tests/simple/unnamed_block_decl.sv
index e81b457a8..e78c577da 100644
--- a/tests/simple/unnamed_block_decl.sv
+++ b/tests/simple/unnamed_block_decl.sv
@@ -1,4 +1,4 @@
-module top(z);
+module unnamed_block_decl(z);
 	output integer z;
 	initial begin
 		integer x;
diff --git a/tests/simple/verilog_primitives.v b/tests/simple/verilog_primitives.v
new file mode 100644
index 000000000..0ee07393b
--- /dev/null
+++ b/tests/simple/verilog_primitives.v
@@ -0,0 +1,15 @@
+module verilog_primitives (
+	input wire in1, in2, in3,
+	output wire out_buf0, out_buf1, out_buf2, out_buf3, out_buf4,
+	output wire out_not0, out_not1, out_not2,
+	output wire out_xnor
+);
+
+buf u_buf0 (out_buf0, in1);
+buf u_buf1 (out_buf1, out_buf2, out_buf3, out_buf4, in2);
+
+not u_not0 (out_not0, out_not1, out_not2, in1);
+
+xnor u_xnor0 (out_xnor, in1, in2, in3);
+
+endmodule
diff --git a/tests/simple/vloghammer.v b/tests/simple/vloghammer.v
index 3bb3cf992..5fcedbff1 100644
--- a/tests/simple/vloghammer.v
+++ b/tests/simple/vloghammer.v
@@ -1,6 +1,6 @@
 
 // test cases found using vloghammer
-// https://github.com/cliffordwolf/VlogHammer
+// https://github.com/YosysHQ/VlogHammer
 
 module test01(a, y);
   input [7:0] a;
diff --git a/tests/simple/wandwor.v b/tests/simple/wandwor.v
index 34404aa26..40502acfc 100644
--- a/tests/simple/wandwor.v
+++ b/tests/simple/wandwor.v
@@ -5,9 +5,9 @@ module wandwor_test0 (A, B, C, D, X, Y, Z);
 	output Z;
 
 	assign X = A, X = B, Y = C, Y = D;
-	foo foo_0 (C, D, X);
-	foo foo_1 (A, B, Y);
-	foo foo_2 (X, Y, Z);
+	wandwor_foo foo_0 (C, D, X);
+	wandwor_foo foo_1 (A, B, Y);
+	wandwor_foo foo_2 (X, Y, Z);
 endmodule
 
 module wandwor_test1 (A, B, C, D, X, Y, Z);
@@ -16,7 +16,7 @@ module wandwor_test1 (A, B, C, D, X, Y, Z);
 	output wand [3:0] Y;
 	output Z;
 
-	bar bar_inst (
+	wandwor_bar bar_inst (
 		.I0({A, B}),
 		.I1({B, A}),
 		.O({X, Y})
@@ -27,10 +27,10 @@ module wandwor_test1 (A, B, C, D, X, Y, Z);
 	assign Z = ^{X,Y};
 endmodule
 
-module foo(input I0, I1, output O);
+module wandwor_foo(input I0, I1, output O);
 	assign O = I0 ^ I1;
 endmodule
 
-module bar(input [7:0] I0, I1, output [7:0] O);
+module wandwor_bar(input [7:0] I0, I1, output [7:0] O);
 	assign O = I0 + I1;
 endmodule