diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
| commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
| tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /tests/simple/mem2reg.v | |
| parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) | |
| download | yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.gz yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.bz2 yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.zip | |
Fixed trailing whitespaces
Diffstat (limited to 'tests/simple/mem2reg.v')
| -rw-r--r-- | tests/simple/mem2reg.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v index bed5528d4..40f490b75 100644 --- a/tests/simple/mem2reg.v +++ b/tests/simple/mem2reg.v @@ -47,7 +47,7 @@ endmodule // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/ module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b); -reg [7:0] dint_c [0:7]; +reg [7:0] dint_c [0:7]; always @(posedge clk) begin {dout_a[0], dint_c[3]} <= din_a; |