Fixed trailing whitespaces

6 files changed, 10 insertions, 10 deletions

diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py
index 352eedb09..fb5695ff6 100644
--- a/tests/fsm/generate.py
+++ b/tests/fsm/generate.py
@@ -108,4 +108,4 @@ for idx in range(50):
                 print('cd ..')
             print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
             print('sat -verify-no-timeout -timeout 20 -seq 5 -set-at 1 %s_rst 1 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter' % ('gold' if rst2 else 'in'))
- 
+
diff --git a/tests/realmath/generate.py b/tests/realmath/generate.py
index 16f68f052..aee211185 100644
--- a/tests/realmath/generate.py
+++ b/tests/realmath/generate.py
@@ -39,7 +39,7 @@ def random_expression(depth = 3, maxparam = 0):
         return op + '(' + recursion() + ', ' + recursion() + ')'
     raise
 
-for idx in range(100): 
+for idx in range(100):
     with open('temp/uut_%05d.v' % idx, 'w') as f:
         with redirect_stdout(f):
             print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)])))
@@ -91,4 +91,4 @@ for idx in range(100):
                 print('  compare_ref_syn(%2d, r%02d, s%02d);' % (i, i, i))
             print('end')
             print('endmodule')
- 
+
diff --git a/tests/share/generate.py b/tests/share/generate.py
index 7f8a59513..271dd9c40 100644
--- a/tests/share/generate.py
+++ b/tests/share/generate.py
@@ -72,4 +72,4 @@ for idx in range(100):
             print('tee -a temp/all_share_log.txt share -aggressive gate')
             print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
             print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter')
- 
+
diff --git a/tests/simple/loops.v b/tests/simple/loops.v
index 77cdcd8e2..d7743a422 100644
--- a/tests/simple/loops.v
+++ b/tests/simple/loops.v
@@ -41,10 +41,10 @@ begin
 		keysched_last_key_i = key_i;
 	else
 		keysched_last_key_i = keysched_new_key_o;
-	
+
 	if (round == 0 && addroundkey_start_i)
 	begin
-		data_var = addroundkey_data_i;	
+		data_var = addroundkey_data_i;
 		round_key_var = key_i;
 		round_data_var = round_key_var ^ data_var;
 		next_addroundkey_data_reg = round_data_var;
@@ -66,7 +66,7 @@ begin
 	end
 	else if (addroundkey_round == round && keysched_ready_o)
 	begin
-		data_var = addroundkey_data_i;	
+		data_var = addroundkey_data_i;
 		round_key_var = keysched_new_key_o;
 		round_data_var = round_key_var ^ data_var;
 		next_addroundkey_data_reg = round_data_var;
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index bed5528d4..40f490b75 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -47,7 +47,7 @@ endmodule
 
 // http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
 module mem2reg_test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
-reg [7:0] dint_c [0:7]; 
+reg [7:0] dint_c [0:7];
 always @(posedge clk)
   begin
       {dout_a[0], dint_c[3]} <= din_a;
diff --git a/tests/simple/omsp_dbg_uart.v b/tests/simple/omsp_dbg_uart.v
index dc8860dee..569a28adb 100644
--- a/tests/simple/omsp_dbg_uart.v
+++ b/tests/simple/omsp_dbg_uart.v
@@ -22,13 +22,13 @@ always @(uart_state or mem_burst)
     RX_DATA : uart_state_nxt =  RX_SYNC;
     default  : uart_state_nxt =  RX_CMD;
   endcase
-   
+
 always @(posedge dbg_clk or posedge dbg_rst)
   if (dbg_rst) uart_state <= RX_SYNC;
   else if (xfer_done | mem_burst) uart_state <= uart_state_nxt;
 
 assign cmd_valid = (uart_state==RX_CMD) & xfer_done;
 assign xfer_done = uart_state!=RX_SYNC;
-   
+
 endmodule