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| author | whitequark <whitequark@whitequark.org> | 2021-01-28 21:32:27 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-01-28 21:32:27 +0000 |
| commit | 74b0c385200d4282011c372d08e1e64b540d4132 (patch) | |
| tree | 53e1add099b0428b2ce59587d9e99c95102a36b0 /tests/simple/forgen02.v | |
| parent | d0d7a360edb08abf4dce6e37f61eea0a6e6ef045 (diff) | |
| parent | 27257a419fe94e10f24eea916c56821e22e43cc5 (diff) | |
| download | yosys-74b0c385200d4282011c372d08e1e64b540d4132.tar.gz yosys-74b0c385200d4282011c372d08e1e64b540d4132.tar.bz2 yosys-74b0c385200d4282011c372d08e1e64b540d4132.zip | |
Merge pull request #2569 from zachjs/macro-arg-surrounding-spaces
verilog: strip leading and trailing spaces in macro args
Diffstat (limited to 'tests/simple/forgen02.v')
0 files changed, 0 insertions, 0 deletions