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author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-02 13:22:44 +0100 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-02 13:22:44 +0100 |
commit | 7ef6da4c7d418b53ea2868ea452a856cfb2d5b21 (patch) | |
tree | c065022ee3545f3f5830d029d27726ae9d897692 /tests/sat/sim_counter.ys | |
parent | 4a30c9cb9418869b34da3f304c7e3cc72a0ffe62 (diff) | |
download | yosys-7ef6da4c7d418b53ea2868ea452a856cfb2d5b21.tar.gz yosys-7ef6da4c7d418b53ea2868ea452a856cfb2d5b21.tar.bz2 yosys-7ef6da4c7d418b53ea2868ea452a856cfb2d5b21.zip |
Add test cases for co-simulation
Diffstat (limited to 'tests/sat/sim_counter.ys')
-rw-r--r-- | tests/sat/sim_counter.ys | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/tests/sat/sim_counter.ys b/tests/sat/sim_counter.ys new file mode 100644 index 000000000..a0ff41b6e --- /dev/null +++ b/tests/sat/sim_counter.ys @@ -0,0 +1,48 @@ +# Create stimulus file +read_verilog <<EOT +module top (clk, reset, cnt); + +input clk; +input reset; +output [7:0] cnt; + +reg [7:0] cnt; + +endmodule +EOT +prep -top top; +sim -clock clk -reset reset -fst stimulus.fst -n 10 +design -reset + +# Counter implementation +read_verilog <<EOT +module top (clk, reset, cnt); + +input clk; +input reset; +output [7:0] cnt; + +reg [7:0] cnt; + +always @(posedge clk) + if (!reset) + cnt = cnt + 1; + else + cnt = 0; + +endmodule +EOT +prep -top top; + +# Simulate with stimulus +sim -clock clk -scope top -r stimulus.fst + +# Stimulus does not have counter values +# x in FST can match any value in simulation +sim -clock clk -scope top -r stimulus.fst -sim-gate + +# Stimulus does not have counter values +# x in simulation can match any value in FST +# so we expect error +logger -expect error "Signal difference" 1 +sim -clock clk -scope top -r stimulus.fst -sim-gold |