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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-03-09 21:32:16 +0100 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-03-15 17:16:53 +0100 |
commit | 3af871f969f7f5bd5201bac17544559671312a6f (patch) | |
tree | 31425736db665b093e02c90e170644f2325740a5 /tests/opt/opt_clean_init.ys | |
parent | f965b3fa54eb38bf7f0246acc874087fc696f7f5 (diff) | |
download | yosys-3af871f969f7f5bd5201bac17544559671312a6f.tar.gz yosys-3af871f969f7f5bd5201bac17544559671312a6f.tar.bz2 yosys-3af871f969f7f5bd5201bac17544559671312a6f.zip |
opt_clean: Remove init attribute bits together with removed DFFs.
Fixes #2546.
Diffstat (limited to 'tests/opt/opt_clean_init.ys')
-rw-r--r-- | tests/opt/opt_clean_init.ys | 31 |
1 files changed, 20 insertions, 11 deletions
diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys index 0d567608d..7933f3e17 100644 --- a/tests/opt/opt_clean_init.ys +++ b/tests/opt/opt_clean_init.ys @@ -1,13 +1,22 @@ -logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1 -logger -expect-no-warnings -read_verilog <<EOT -module top; -(* init=1'b0 *) wire w = 1'b0; -(* init=1'bx *) wire x = 1'b0; -(* init=1'b1 *) wire y = 1'b0; -(* init=1'b0 *) wire z = 1'bx; +read_verilog << EOT +module top(...); + +input [1:0] D; +input C; +output O; +reg [1:0] Q; + +initial Q = 0; + +always @(posedge C) + Q <= D; + +assign O = Q[1]; + endmodule EOT -clean -select -assert-count 1 a:init -select -assert-count 1 w:y a:init %i + +synth +check -assert -initdrv + +select -assert-count 1 a:init=2'b0x |