Merge pull request #1435 from YosysHQ/mmicko/efinix

Add tests for Efinix architecture (contd)

24 files changed, 556 insertions, 0 deletions

diff --git a/tests/efinix/.gitignore b/tests/efinix/.gitignore
new file mode 100644
index 000000000..b48f808a1
--- /dev/null
+++ b/tests/efinix/.gitignore
@@ -0,0 +1,3 @@
+/*.log
+/*.out
+/run-test.mk
diff --git a/tests/efinix/add_sub.v b/tests/efinix/add_sub.v
new file mode 100644
index 000000000..177c32e30
--- /dev/null
+++ b/tests/efinix/add_sub.v
@@ -0,0 +1,13 @@
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A =  x + y;
+assign B =  x - y;
+
+endmodule
diff --git a/tests/efinix/add_sub.ys b/tests/efinix/add_sub.ys
new file mode 100644
index 000000000..8bd28c68e
--- /dev/null
+++ b/tests/efinix/add_sub.ys
@@ -0,0 +1,10 @@
+read_verilog add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 10 t:EFX_ADD
+select -assert-count 4  t:EFX_LUT4
+select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D
+
diff --git a/tests/efinix/adffs.v b/tests/efinix/adffs.v
new file mode 100644
index 000000000..223b52d21
--- /dev/null
+++ b/tests/efinix/adffs.v
@@ -0,0 +1,47 @@
+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module dffs
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk )
+		if ( !clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys
new file mode 100644
index 000000000..791626428
--- /dev/null
+++ b/tests/efinix/adffs.ys
@@ -0,0 +1,50 @@
+read_verilog adffs.v
+design -save read
+
+hierarchy -top adff
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
+
+
+design -load read
+hierarchy -top adffn
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
+
+
+design -load read
+hierarchy -top dffs
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top ndffnr
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
diff --git a/tests/efinix/counter.v b/tests/efinix/counter.v
new file mode 100644
index 000000000..52852f8ac
--- /dev/null
+++ b/tests/efinix/counter.v
@@ -0,0 +1,17 @@
+module top    (

+out,

+clk,

+reset

+);

+    output [7:0] out;

+    input clk, reset;

+    reg [7:0] out;

+

+    always @(posedge clk, posedge reset)

+		if (reset) begin

+			out <= 8'b0 ;

+		end else

+			out <= out + 1;

+

+

+endmodule

diff --git a/tests/efinix/counter.ys b/tests/efinix/counter.ys
new file mode 100644
index 000000000..82e61d39b
--- /dev/null
+++ b/tests/efinix/counter.ys
@@ -0,0 +1,12 @@
+read_verilog counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 8 t:EFX_FF
+select -assert-count 9 t:EFX_ADD
+select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D
diff --git a/tests/efinix/dffs.v b/tests/efinix/dffs.v
new file mode 100644
index 000000000..3418787c9
--- /dev/null
+++ b/tests/efinix/dffs.v
@@ -0,0 +1,15 @@
+module dff
+    ( input d, clk, output reg q );
+	always @( posedge clk )
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule
diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys
new file mode 100644
index 000000000..cdd288233
--- /dev/null
+++ b/tests/efinix/dffs.ys
@@ -0,0 +1,24 @@
+read_verilog dffs.v
+design -save read
+
+hierarchy -top dff
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D
+
+design -load read
+hierarchy -top dffe
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_FF
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D
diff --git a/tests/efinix/fsm.v b/tests/efinix/fsm.v
new file mode 100644
index 000000000..368fbaace
--- /dev/null
+++ b/tests/efinix/fsm.v
@@ -0,0 +1,55 @@
+ module fsm (

+ clock,

+ reset,

+ req_0,

+ req_1,

+ gnt_0,

+ gnt_1

+ );

+ input   clock,reset,req_0,req_1;

+ output  gnt_0,gnt_1;

+ wire    clock,reset,req_0,req_1;

+ reg     gnt_0,gnt_1;

+

+ parameter SIZE = 3           ;

+ parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;

+

+ reg [SIZE-1:0] state;

+ reg [SIZE-1:0] next_state;

+

+ always @ (posedge clock)

+ begin : FSM

+ if (reset == 1'b1) begin

+   state <=  #1  IDLE;

+   gnt_0 <= 0;

+   gnt_1 <= 0;

+ end else

+  case(state)

+    IDLE : if (req_0 == 1'b1) begin

+                 state <=  #1  GNT0;

+                 gnt_0 <= 1;

+               end else if (req_1 == 1'b1) begin

+                 gnt_1 <= 1;

+                 state <=  #1  GNT0;

+               end else begin

+                 state <=  #1  IDLE;

+               end

+    GNT0 : if (req_0 == 1'b1) begin

+                 state <=  #1  GNT0;

+               end else begin

+                 gnt_0 <= 0;

+                 state <=  #1  IDLE;

+               end

+    GNT1 : if (req_1 == 1'b1) begin

+                 state <=  #1  GNT2;

+				 gnt_1 <= req_0;

+               end

+    GNT2 : if (req_0 == 1'b1) begin

+                 state <=  #1  GNT1;

+				 gnt_1 <= req_1;

+               end

+    default : state <=  #1  IDLE;

+ endcase

+ end

+

+endmodule

diff --git a/tests/efinix/fsm.ys b/tests/efinix/fsm.ys
new file mode 100644
index 000000000..2ec75215d
--- /dev/null
+++ b/tests/efinix/fsm.ys
@@ -0,0 +1,14 @@
+read_verilog fsm.v
+hierarchy -top fsm
+proc
+flatten
+#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
+#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd fsm # Constrain all select calls below inside the top module
+
+select -assert-count 1  t:EFX_GBUFCE
+select -assert-count 6  t:EFX_FF
+select -assert-count 15 t:EFX_LUT4
+select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D
diff --git a/tests/efinix/latches.v b/tests/efinix/latches.v
new file mode 100644
index 000000000..adb5d5319
--- /dev/null
+++ b/tests/efinix/latches.v
@@ -0,0 +1,24 @@
+module latchp
+    ( input d, clk, en, output reg q );
+	always @*
+		if ( en )
+			q <= d;
+endmodule
+
+module latchn
+    ( input d, clk, en, output reg q );
+	always @*
+		if ( !en )
+			q <= d;
+endmodule
+
+module latchsr
+    ( input d, clk, en, clr, pre, output reg q );
+	always @*
+		if ( clr )
+			q <= 1'b0;
+		else if ( pre )
+			q <= 1'b1;
+		else if ( en )
+			q <= d;
+endmodule
diff --git a/tests/efinix/latches.ys b/tests/efinix/latches.ys
new file mode 100644
index 000000000..899d024ce
--- /dev/null
+++ b/tests/efinix/latches.ys
@@ -0,0 +1,33 @@
+read_verilog latches.v
+design -save read
+
+hierarchy -top latchp
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_efinix
+cd latchp # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchn
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_efinix
+cd latchn # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+
+design -load read
+hierarchy -top latchsr
+proc
+# Can't run any sort of equivalence check because latches are blown to LUTs
+synth_efinix
+cd latchsr # Constrain all select calls below inside the top module
+select -assert-count 2 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
diff --git a/tests/efinix/logic.v b/tests/efinix/logic.v
new file mode 100644
index 000000000..e5343cae0
--- /dev/null
+++ b/tests/efinix/logic.v
@@ -0,0 +1,18 @@
+module top
+(
+ input [0:7] in,
+ output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
+ );
+
+   assign     B1 =  in[0] & in[1];
+   assign     B2 =  in[0] | in[1];
+   assign     B3 =  in[0] ~& in[1];
+   assign     B4 =  in[0] ~| in[1];
+   assign     B5 =  in[0] ^ in[1];
+   assign     B6 =  in[0] ~^ in[1];
+   assign     B7 =  ~in[0];
+   assign     B8 =  in[0];
+   assign     B9 =  in[0:1] && in [2:3];
+   assign     B10 =  in[0:1] || in [2:3];
+
+endmodule
diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys
new file mode 100644
index 000000000..fdedb337b
--- /dev/null
+++ b/tests/efinix/logic.ys
@@ -0,0 +1,9 @@
+read_verilog logic.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 9 t:EFX_LUT4
+select -assert-none t:EFX_LUT4 %% t:* %D
diff --git a/tests/efinix/memory.v b/tests/efinix/memory.v
new file mode 100644
index 000000000..5634d6507
--- /dev/null
+++ b/tests/efinix/memory.v
@@ -0,0 +1,21 @@
+module top
+(
+	input [7:0] data_a,
+	input [8:1] addr_a,
+	input we_a, clk,
+	output reg [7:0] q_a
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		q_a <= ram[addr_a];
+	end
+endmodule
diff --git a/tests/efinix/memory.ys b/tests/efinix/memory.ys
new file mode 100644
index 000000000..fe24b0a9b
--- /dev/null
+++ b/tests/efinix/memory.ys
@@ -0,0 +1,18 @@
+read_verilog memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#ERROR: Called with -verify and proof did fail!
+#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 1 t:EFX_RAM_5K
+select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D
diff --git a/tests/efinix/mux.v b/tests/efinix/mux.v
new file mode 100644
index 000000000..27bc0bf0b
--- /dev/null
+++ b/tests/efinix/mux.v
@@ -0,0 +1,65 @@
+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
diff --git a/tests/efinix/mux.ys b/tests/efinix/mux.ys
new file mode 100644
index 000000000..71a9681de
--- /dev/null
+++ b/tests/efinix/mux.ys
@@ -0,0 +1,41 @@
+read_verilog mux.v
+design -save read
+
+hierarchy -top mux2
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux2 # Constrain all select calls below inside the top module
+select -assert-count 1 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux4
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux4 # Constrain all select calls below inside the top module
+select -assert-count 2 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux8
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux8 # Constrain all select calls below inside the top module
+select -assert-count 5 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
+
+design -load read
+hierarchy -top mux16
+proc
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd mux16 # Constrain all select calls below inside the top module
+select -assert-count 12 t:EFX_LUT4
+
+select -assert-none t:EFX_LUT4 %% t:* %D
diff --git a/tests/efinix/run-test.sh b/tests/efinix/run-test.sh
new file mode 100755
index 000000000..46716f9a0
--- /dev/null
+++ b/tests/efinix/run-test.sh
@@ -0,0 +1,20 @@
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+	echo "all:: run-$x"
+	echo "run-$x:"
+	echo "	@echo 'Running $x..'"
+	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
+done
+for s in *.sh; do
+	if [ "$s" != "run-test.sh" ]; then
+		echo "all:: run-$s"
+		echo "run-$s:"
+		echo "	@echo 'Running $s..'"
+		echo "	@bash $s"
+	fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v
new file mode 100644
index 000000000..ce2c81dd2
--- /dev/null
+++ b/tests/efinix/shifter.v
@@ -0,0 +1,16 @@
+module top    (

+out,

+clk,

+in

+);

+    output [7:0] out;

+    input signed clk, in;

+    reg signed [7:0] out = 0;

+

+    always @(posedge clk)

+	begin

+		out    <= out << 1;

+		out[7] <= in;

+	end

+

+endmodule

diff --git a/tests/efinix/shifter.ys b/tests/efinix/shifter.ys
new file mode 100644
index 000000000..1a6b5565c
--- /dev/null
+++ b/tests/efinix/shifter.ys
@@ -0,0 +1,11 @@
+read_verilog shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1  t:EFX_GBUFCE
+select -assert-count 8  t:EFX_FF
+select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D
diff --git a/tests/efinix/tribuf.v b/tests/efinix/tribuf.v
new file mode 100644
index 000000000..c64468253
--- /dev/null
+++ b/tests/efinix/tribuf.v
@@ -0,0 +1,8 @@
+module tristate (en, i, o);
+    input en;
+    input i;
+    output reg o;
+    
+    always @(en or i)
+		o <= (en)? i : 1'bZ;
+endmodule
diff --git a/tests/efinix/tribuf.ys b/tests/efinix/tribuf.ys
new file mode 100644
index 000000000..2e2ab9e65
--- /dev/null
+++ b/tests/efinix/tribuf.ys
@@ -0,0 +1,12 @@
+read_verilog tribuf.v
+hierarchy -top tristate
+proc
+tribuf
+flatten
+synth
+equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd tristate # Constrain all select calls below inside the top module
+#Internal cell type used. Need support it.
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D