diff options
| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:35 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:35 +0200 |
| commit | 0568920d7916b7356db216210398f8940d426f0d (patch) | |
| tree | a625838a0efbfb0176a57887c208467a7addd0a6 /tests/efinix/memory.v | |
| parent | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (diff) | |
| parent | b4d765054897f7ee388b54d907fd8ce607db2d58 (diff) | |
| download | yosys-0568920d7916b7356db216210398f8940d426f0d.tar.gz yosys-0568920d7916b7356db216210398f8940d426f0d.tar.bz2 yosys-0568920d7916b7356db216210398f8940d426f0d.zip | |
Merge pull request #1435 from YosysHQ/mmicko/efinix
Add tests for Efinix architecture (contd)
Diffstat (limited to 'tests/efinix/memory.v')
| -rw-r--r-- | tests/efinix/memory.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/efinix/memory.v b/tests/efinix/memory.v new file mode 100644 index 000000000..5634d6507 --- /dev/null +++ b/tests/efinix/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [8:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule |