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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 10:54:35 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 10:54:35 +0200 |
| commit | 0568920d7916b7356db216210398f8940d426f0d (patch) | |
| tree | a625838a0efbfb0176a57887c208467a7addd0a6 /tests/efinix/add_sub.ys | |
| parent | ab4899a2d02b994d79e4aa223eb743793b9a60b3 (diff) | |
| parent | b4d765054897f7ee388b54d907fd8ce607db2d58 (diff) | |
| download | yosys-0568920d7916b7356db216210398f8940d426f0d.tar.gz yosys-0568920d7916b7356db216210398f8940d426f0d.tar.bz2 yosys-0568920d7916b7356db216210398f8940d426f0d.zip | |
Merge pull request #1435 from YosysHQ/mmicko/efinix
Add tests for Efinix architecture (contd)
Diffstat (limited to 'tests/efinix/add_sub.ys')
| -rw-r--r-- | tests/efinix/add_sub.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/efinix/add_sub.ys b/tests/efinix/add_sub.ys new file mode 100644 index 000000000..8bd28c68e --- /dev/null +++ b/tests/efinix/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:EFX_ADD +select -assert-count 4 t:EFX_LUT4 +select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D + |