Moved all tests in arch sub directory

32 files changed, 0 insertions, 668 deletions

diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore
deleted file mode 100644
index 1d329c933..000000000
--- a/tests/ecp5/.gitignore
+++ /dev/null
@@ -1,2 +0,0 @@
-*.log
-/run-test.mk
diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v
deleted file mode 100644
index 177c32e30..000000000
--- a/tests/ecp5/add_sub.v
+++ /dev/null
@@ -1,13 +0,0 @@
-module top
-(
- input [3:0] x,
- input [3:0] y,
-
- output [3:0] A,
- output [3:0] B
- );
-
-assign A =  x + y;
-assign B =  x - y;
-
-endmodule
diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys
deleted file mode 100644
index ee72d732f..000000000
--- a/tests/ecp5/add_sub.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog add_sub.v
-hierarchy -top top
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 10 t:LUT4
-select -assert-none t:LUT4 %% t:* %D
-
diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v
deleted file mode 100644
index 223b52d21..000000000
--- a/tests/ecp5/adffs.v
+++ /dev/null
@@ -1,47 +0,0 @@
-module adff
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, posedge clr )
-		if ( clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module adffn
-    ( input d, clk, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk, negedge clr )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
-
-module dffs
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( pre )
-			q <= 1'b1;
-		else
-            q <= d;
-endmodule
-
-module ndffnr
-    ( input d, clk, pre, clr, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( negedge clk )
-		if ( !clr )
-			q <= 1'b0;
-		else
-            q <= d;
-endmodule
diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys
deleted file mode 100644
index c6780e565..000000000
--- a/tests/ecp5/adffs.ys
+++ /dev/null
@@ -1,40 +0,0 @@
-read_verilog adffs.v
-design -save read
-
-hierarchy -top adff
-proc
-equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd adff # Constrain all select calls below inside the top module
-select -assert-count 1 t:TRELLIS_FF
-select -assert-none t:TRELLIS_FF %% t:* %D
-
-design -load read
-hierarchy -top adffn
-proc
-equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd adffn # Constrain all select calls below inside the top module
-select -assert-count 1 t:TRELLIS_FF
-select -assert-count 1 t:LUT4
-select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
-
-design -load read
-hierarchy -top dffs
-proc
-equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffs # Constrain all select calls below inside the top module
-select -assert-count 1 t:TRELLIS_FF
-select -assert-count 1 t:LUT4
-select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
-
-design -load read
-hierarchy -top ndffnr
-proc
-equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd ndffnr # Constrain all select calls below inside the top module
-select -assert-count 1 t:TRELLIS_FF
-select -assert-count 1 t:LUT4
-select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v
deleted file mode 100644
index 52852f8ac..000000000
--- a/tests/ecp5/counter.v
+++ /dev/null
@@ -1,17 +0,0 @@
-module top    (

-out,

-clk,

-reset

-);

-    output [7:0] out;

-    input clk, reset;

-    reg [7:0] out;

-

-    always @(posedge clk, posedge reset)

-		if (reset) begin

-			out <= 8'b0 ;

-		end else

-			out <= out + 1;

-

-

-endmodule

diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys
deleted file mode 100644
index 8ef70778f..000000000
--- a/tests/ecp5/counter.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog counter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 4 t:CCU2C
-select -assert-count 8 t:TRELLIS_FF
-select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D
diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v
deleted file mode 100644
index 3418787c9..000000000
--- a/tests/ecp5/dffs.v
+++ /dev/null
@@ -1,15 +0,0 @@
-module dff
-    ( input d, clk, output reg q );
-	always @( posedge clk )
-            q <= d;
-endmodule
-
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys
deleted file mode 100644
index a4f45d2fb..000000000
--- a/tests/ecp5/dffs.ys
+++ /dev/null
@@ -1,19 +0,0 @@
-read_verilog dffs.v
-design -save read
-
-hierarchy -top dff
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dff # Constrain all select calls below inside the top module
-select -assert-count 1 t:TRELLIS_FF
-select -assert-none t:TRELLIS_FF %% t:* %D
-
-design -load read
-hierarchy -top dffe
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd dffe # Constrain all select calls below inside the top module
-select -assert-count 1 t:TRELLIS_FF
-select -assert-none t:TRELLIS_FF %% t:* %D
\ No newline at end of file
diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v
deleted file mode 100644
index 3ea4c1f27..000000000
--- a/tests/ecp5/dpram.v
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
-Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
-*/
-module top (din, write_en, waddr, wclk, raddr, rclk, dout);
-parameter addr_width = 8;
-parameter data_width = 8;
-input [addr_width-1:0] waddr, raddr;
-input [data_width-1:0] din;
-input write_en, wclk, rclk;
-output [data_width-1:0] dout;
-reg [data_width-1:0] dout;
-reg [data_width-1:0] mem [(1<<addr_width)-1:0]
-/* synthesis syn_ramstyle = "no_rw_check" */ ;
-always @(posedge wclk) // Write memory.
-begin
-if (write_en)
-mem[waddr] <= din; // Using write address bus.
-end
-always @(posedge rclk) // Read memory.
-begin
-dout <= mem[raddr]; // Using read address bus.
-end
-endmodule
diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys
deleted file mode 100644
index 3bc6bc1d0..000000000
--- a/tests/ecp5/dpram.ys
+++ /dev/null
@@ -1,18 +0,0 @@
-read_verilog dpram.v
-hierarchy -top top
-proc
-memory -nomap
-equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-
-#Blocked by issue #1358 (Missing ECP5 simulation models)
-#ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database.
-#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd top
-select -assert-count 1 t:DP16KD
-select -assert-none t:DP16KD %% t:* %D
diff --git a/tests/ecp5/fsm.v b/tests/ecp5/fsm.v
deleted file mode 100644
index 368fbaace..000000000
--- a/tests/ecp5/fsm.v
+++ /dev/null
@@ -1,55 +0,0 @@
- module fsm (

- clock,

- reset,

- req_0,

- req_1,

- gnt_0,

- gnt_1

- );

- input   clock,reset,req_0,req_1;

- output  gnt_0,gnt_1;

- wire    clock,reset,req_0,req_1;

- reg     gnt_0,gnt_1;

-

- parameter SIZE = 3           ;

- parameter IDLE  = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;

-

- reg [SIZE-1:0] state;

- reg [SIZE-1:0] next_state;

-

- always @ (posedge clock)

- begin : FSM

- if (reset == 1'b1) begin

-   state <=  #1  IDLE;

-   gnt_0 <= 0;

-   gnt_1 <= 0;

- end else

-  case(state)

-    IDLE : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-                 gnt_0 <= 1;

-               end else if (req_1 == 1'b1) begin

-                 gnt_1 <= 1;

-                 state <=  #1  GNT0;

-               end else begin

-                 state <=  #1  IDLE;

-               end

-    GNT0 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT0;

-               end else begin

-                 gnt_0 <= 0;

-                 state <=  #1  IDLE;

-               end

-    GNT1 : if (req_1 == 1'b1) begin

-                 state <=  #1  GNT2;

-				 gnt_1 <= req_0;

-               end

-    GNT2 : if (req_0 == 1'b1) begin

-                 state <=  #1  GNT1;

-				 gnt_1 <= req_1;

-               end

-    default : state <=  #1  IDLE;

- endcase

- end

-

-endmodule

diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys
deleted file mode 100644
index ded91e5f7..000000000
--- a/tests/ecp5/fsm.ys
+++ /dev/null
@@ -1,12 +0,0 @@
-read_verilog fsm.v
-hierarchy -top fsm
-proc
-flatten
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd fsm # Constrain all select calls below inside the top module
-select -assert-count 1 t:L6MUX21
-select -assert-count 13 t:LUT4
-select -assert-count 5 t:PFUMX
-select -assert-count 5 t:TRELLIS_FF
-select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D
diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v
deleted file mode 100644
index adb5d5319..000000000
--- a/tests/ecp5/latches.v
+++ /dev/null
@@ -1,24 +0,0 @@
-module latchp
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( en )
-			q <= d;
-endmodule
-
-module latchn
-    ( input d, clk, en, output reg q );
-	always @*
-		if ( !en )
-			q <= d;
-endmodule
-
-module latchsr
-    ( input d, clk, en, clr, pre, output reg q );
-	always @*
-		if ( clr )
-			q <= 1'b0;
-		else if ( pre )
-			q <= 1'b1;
-		else if ( en )
-			q <= d;
-endmodule
diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys
deleted file mode 100644
index fc15a6910..000000000
--- a/tests/ecp5/latches.ys
+++ /dev/null
@@ -1,35 +0,0 @@
-
-read_verilog latches.v
-design -save read
-
-hierarchy -top latchp
-proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
-cd latchp # Constrain all select calls below inside the top module
-select -assert-count 1 t:LUT4
-
-select -assert-none t:LUT4 %% t:* %D
-
-
-design -load read
-hierarchy -top latchn
-proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
-cd latchn # Constrain all select calls below inside the top module
-select -assert-count 1 t:LUT4
-
-select -assert-none t:LUT4 %% t:* %D
-
-
-design -load read
-hierarchy -top latchsr
-proc
-# Can't run any sort of equivalence check because latches are blown to LUTs
-synth_ecp5
-cd latchsr # Constrain all select calls below inside the top module
-select -assert-count 2 t:LUT4
-select -assert-count 1 t:PFUMX
-
-select -assert-none t:LUT4 t:PFUMX %% t:* %D
diff --git a/tests/ecp5/logic.v b/tests/ecp5/logic.v
deleted file mode 100644
index e5343cae0..000000000
--- a/tests/ecp5/logic.v
+++ /dev/null
@@ -1,18 +0,0 @@
-module top
-(
- input [0:7] in,
- output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10
- );
-
-   assign     B1 =  in[0] & in[1];
-   assign     B2 =  in[0] | in[1];
-   assign     B3 =  in[0] ~& in[1];
-   assign     B4 =  in[0] ~| in[1];
-   assign     B5 =  in[0] ^ in[1];
-   assign     B6 =  in[0] ~^ in[1];
-   assign     B7 =  ~in[0];
-   assign     B8 =  in[0];
-   assign     B9 =  in[0:1] && in [2:3];
-   assign     B10 =  in[0:1] || in [2:3];
-
-endmodule
diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys
deleted file mode 100644
index 4f113a130..000000000
--- a/tests/ecp5/logic.ys
+++ /dev/null
@@ -1,8 +0,0 @@
-read_verilog logic.v
-hierarchy -top top
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 9 t:LUT4
-select -assert-none t:LUT4 %% t:* %D
diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v
deleted file mode 100644
index 63a3d3a74..000000000
--- a/tests/ecp5/macc.v
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
-Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 77].
-*/
-module top(clk,a,b,c,set);
-parameter A_WIDTH = 4;
-parameter B_WIDTH = 3;
-input set;
-input clk;
-input signed [(A_WIDTH - 1):0] a;
-input signed [(B_WIDTH - 1):0] b;
-output signed [(A_WIDTH + B_WIDTH - 1):0] c;
-reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c;
-assign c = reg_tmp_c;
-always @(posedge clk)
-begin
-if(set)
-begin
-reg_tmp_c <= 0;
-end
-else
-begin
-reg_tmp_c <= a * b + c;
-end
-end
-endmodule
diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys
deleted file mode 100644
index 1863ea4d2..000000000
--- a/tests/ecp5/macc.ys
+++ /dev/null
@@ -1,13 +0,0 @@
-read_verilog macc.v
-hierarchy -top top
-proc
-# Blocked by issue #1358 (Missing ECP5 simulation models)
-#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:MULT18X18D
-select -assert-count 4 t:CCU2C
-select -assert-count 7 t:TRELLIS_FF
-
-select -assert-none t:CCU2C t:MULT18X18D t:TRELLIS_FF %% t:* %D
diff --git a/tests/ecp5/memory.v b/tests/ecp5/memory.v
deleted file mode 100644
index cb7753f7b..000000000
--- a/tests/ecp5/memory.v
+++ /dev/null
@@ -1,21 +0,0 @@
-module top
-(
-	input [7:0] data_a,
-	input [6:1] addr_a,
-	input we_a, clk,
-	output reg [7:0] q_a
-);
-	// Declare the RAM variable
-	reg [7:0] ram[63:0];
-
-	// Port A
-	always @ (posedge clk)
-	begin
-		if (we_a)
-		begin
-			ram[addr_a] <= data_a;
-			q_a <= data_a;
-		end
-		q_a <= ram[addr_a];
-	end
-endmodule
diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys
deleted file mode 100644
index 9b475f122..000000000
--- a/tests/ecp5/memory.ys
+++ /dev/null
@@ -1,19 +0,0 @@
-read_verilog memory.v
-hierarchy -top top
-proc
-memory -nomap
-equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
-cd top
-select -assert-count 24 t:L6MUX21
-select -assert-count 71 t:LUT4
-select -assert-count 32 t:PFUMX
-select -assert-count 8 t:TRELLIS_DPR16X4
-select -assert-count 35 t:TRELLIS_FF
-select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D
diff --git a/tests/ecp5/mul.v b/tests/ecp5/mul.v
deleted file mode 100644
index d5b48b1d7..000000000
--- a/tests/ecp5/mul.v
+++ /dev/null
@@ -1,11 +0,0 @@
-module top
-(
- input [5:0] x,
- input [5:0] y,
-
- output [11:0] A,
- );
-
-assign A =  x * y;
-
-endmodule
diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys
deleted file mode 100644
index 0a91f892e..000000000
--- a/tests/ecp5/mul.ys
+++ /dev/null
@@ -1,11 +0,0 @@
-read_verilog mul.v
-hierarchy -top top
-proc
-# Blocked by issue #1358 (Missing ECP5 simulation models)
-#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 1 t:MULT18X18D
-select -assert-none t:MULT18X18D %% t:* %D
diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v
deleted file mode 100644
index 782424a9b..000000000
--- a/tests/ecp5/mux.v
+++ /dev/null
@@ -1,66 +0,0 @@
-module mux2 (S,A,B,Y);
-    input S;
-    input A,B;
-    output reg Y;
-
-    always @(*)
-		Y = (S)? B : A;
-endmodule
-
-module mux4 ( S, D, Y );
-
-input[1:0] S;
-input[3:0] D;
-output Y;
-
-reg Y;
-wire[1:0] S;
-wire[3:0] D;
-
-always @*
-begin
-    case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-   endcase
-end
-
-endmodule
-
-module mux8 ( S, D, Y );
-
-input[2:0] S;
-input[7:0] D;
-output Y;
-
-reg Y;
-wire[2:0] S;
-wire[7:0] D;
-
-always @*
-begin
-   case( S )
-       0 : Y = D[0];
-       1 : Y = D[1];
-       2 : Y = D[2];
-       3 : Y = D[3];
-       4 : Y = D[4];
-       5 : Y = D[5];
-       6 : Y = D[6];
-       7 : Y = D[7];
-   endcase
-end
-
-endmodule
-
-module mux16 (D, S, Y);
- 	input  [15:0] D;
- 	input  [3:0] S;
- 	output Y;
-
-assign Y = D[S];
-
-endmodule
-
diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys
deleted file mode 100644
index 8cfbd541b..000000000
--- a/tests/ecp5/mux.ys
+++ /dev/null
@@ -1,46 +0,0 @@
-read_verilog mux.v
-design -save read
-
-hierarchy -top mux2
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux2 # Constrain all select calls below inside the top module
-select -assert-count 1 t:LUT4
-select -assert-none t:LUT4 %% t:* %D
-
-design -load read
-hierarchy -top mux4
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux4 # Constrain all select calls below inside the top module
-select -assert-count 1 t:L6MUX21
-select -assert-count 4 t:LUT4
-select -assert-count 2 t:PFUMX
-
-select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
-
-design -load read
-hierarchy -top mux8
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux8 # Constrain all select calls below inside the top module
-select -assert-count 1 t:L6MUX21
-select -assert-count 7 t:LUT4
-select -assert-count 2 t:PFUMX
-
-select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
-
-design -load read
-hierarchy -top mux16
-proc
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 8 t:L6MUX21
-select -assert-count 26 t:LUT4
-select -assert-count 12 t:PFUMX
-
-select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D
diff --git a/tests/ecp5/rom.v b/tests/ecp5/rom.v
deleted file mode 100644
index 0a0f41f37..000000000
--- a/tests/ecp5/rom.v
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
-Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 74].
-*/
-module top(data, addr);
-output [3:0] data;
-input [4:0] addr;
-always @(addr) begin
-case (addr)
-0 : data = 'h4;
-1 : data = 'h9;
-2 : data = 'h1;
-15 : data = 'h8;
-16 : data = 'h1;
-17 : data = 'h0;
-default : data = 'h0;
-endcase
-end
-endmodule
diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys
deleted file mode 100644
index 98645ae43..000000000
--- a/tests/ecp5/rom.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog rom.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 6 t:LUT4
-select -assert-count 3 t:PFUMX
-select -assert-none t:LUT4 t:PFUMX %% t:* %D
diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh
deleted file mode 100755
index 46716f9a0..000000000
--- a/tests/ecp5/run-test.sh
+++ /dev/null
@@ -1,20 +0,0 @@
-#!/usr/bin/env bash
-set -e
-{
-echo "all::"
-for x in *.ys; do
-	echo "all:: run-$x"
-	echo "run-$x:"
-	echo "	@echo 'Running $x..'"
-	echo "	@../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x"
-done
-for s in *.sh; do
-	if [ "$s" != "run-test.sh" ]; then
-		echo "all:: run-$s"
-		echo "run-$s:"
-		echo "	@echo 'Running $s..'"
-		echo "	@bash $s"
-	fi
-done
-} > run-test.mk
-exec ${MAKE:-make} -f run-test.mk
diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v
deleted file mode 100644
index 04ae49d83..000000000
--- a/tests/ecp5/shifter.v
+++ /dev/null
@@ -1,16 +0,0 @@
-module top    (

-out,

-clk,

-in

-);

-    output [7:0] out;

-    input signed clk, in;

-    reg signed [7:0] out = 0;

-

-    always @(posedge clk)

-	begin

-		out    <= out >> 1;

-		out[7] <= in;

-	end

-

-endmodule

diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys
deleted file mode 100644
index e1901e1a8..000000000
--- a/tests/ecp5/shifter.ys
+++ /dev/null
@@ -1,10 +0,0 @@
-read_verilog shifter.v
-hierarchy -top top
-proc
-flatten
-equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
- 
-select -assert-count 8 t:TRELLIS_FF
-select -assert-none t:TRELLIS_FF %% t:* %D
diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v
deleted file mode 100644
index 90dd314e4..000000000
--- a/tests/ecp5/tribuf.v
+++ /dev/null
@@ -1,8 +0,0 @@
-module tristate (en, i, o);
-    input en;
-    input i;
-    output o;
-
-	assign o = en ? i : 1'bz;
-
-endmodule
diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys
deleted file mode 100644
index a6e9c9598..000000000
--- a/tests/ecp5/tribuf.ys
+++ /dev/null
@@ -1,9 +0,0 @@
-read_verilog tribuf.v
-hierarchy -top tristate
-proc
-flatten
-equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check
-design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd tristate # Constrain all select calls below inside the top module
-select -assert-count 1 t:$_TBUF_
-select -assert-none t:$_TBUF_ %% t:* %D