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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-28 09:47:03 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-28 09:47:03 +0300 |
| commit | 2270ead09fb4695442c66fe5c06445235f390f2b (patch) | |
| tree | 31d55d4e9a9b8af8ca515777af28df492e86f2af /tests/ecp5/dpram.ys | |
| parent | 980830f7b82f2a974f43580f61e917f99fbb4e7e (diff) | |
| download | yosys-2270ead09fb4695442c66fe5c06445235f390f2b.tar.gz yosys-2270ead09fb4695442c66fe5c06445235f390f2b.tar.bz2 yosys-2270ead09fb4695442c66fe5c06445235f390f2b.zip | |
Add tests for ecp5
Diffstat (limited to 'tests/ecp5/dpram.ys')
| -rw-r--r-- | tests/ecp5/dpram.ys | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys new file mode 100644 index 000000000..7762ce788 --- /dev/null +++ b/tests/ecp5/dpram.ys @@ -0,0 +1,18 @@ +read_verilog dpram.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:DP16KD +select -assert-none t:DP16KD %% t:* %D +write_verilog dpram_synth.v |