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authorSahand Kashani <sahand.kashani@gmail.com>2020-04-08 23:50:37 +0200
committerSahand Kashani <sahand.kashani@gmail.com>2020-04-08 23:50:37 +0200
commit9edf8869c18951ec2b75f074065f073da3253244 (patch)
tree09fba95ba6d3f93ecab828c84b9ff3f74160d7b9 /tests/arch
parent820e3d1dad4f484f9646588f79b73b21b495e3d8 (diff)
parent5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff)
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Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
Diffstat (limited to 'tests/arch')
-rw-r--r--tests/arch/anlogic/fsm.ys5
-rw-r--r--tests/arch/efinix/fsm.ys5
2 files changed, 3 insertions, 7 deletions
diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys
index 0bcc4e011..eb94177ad 100644
--- a/tests/arch/anlogic/fsm.ys
+++ b/tests/arch/anlogic/fsm.ys
@@ -10,9 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
-select -assert-count 1 t:AL_MAP_LUT2
-select -assert-count 5 t:AL_MAP_LUT5
-select -assert-count 1 t:AL_MAP_LUT6
select -assert-count 6 t:AL_MAP_SEQ
-select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
+select -assert-none t:AL_MAP_LUT* t:AL_MAP_SEQ %% t:* %D
diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys
index a2db2ad98..aef720d46 100644
--- a/tests/arch/efinix/fsm.ys
+++ b/tests/arch/efinix/fsm.ys
@@ -10,7 +10,6 @@ sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module
-select -assert-count 1 t:EFX_GBUFCE
-select -assert-count 6 t:EFX_FF
-select -assert-count 15 t:EFX_LUT4
+select -assert-count 1 t:EFX_GBUFCE
+select -assert-count 6 t:EFX_FF
select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D