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-rw-r--r--tests/arch/efinix/lutram.ys13
1 files changed, 1 insertions, 12 deletions
diff --git a/tests/arch/efinix/lutram.ys b/tests/arch/efinix/lutram.ys
index dcf647ce0..8412d1389 100644
--- a/tests/arch/efinix/lutram.ys
+++ b/tests/arch/efinix/lutram.ys
@@ -1,17 +1,6 @@
read_verilog ../common/lutram.v
hierarchy -top lutram_1w1r
-proc
-memory -nomap
-equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix
-memory
-opt -full
-
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-#ERROR: Called with -verify and proof did fail!
-#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
-sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
-
-design -load postopt
+synth_efinix
cd lutram_1w1r
select -assert-count 1 t:EFX_GBUFCE
select -assert-count 1 t:EFX_RAM_5K