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authorMiodrag Milanovic <mmicko@gmail.com>2019-12-28 16:12:45 +0100
committerMiodrag Milanovic <mmicko@gmail.com>2019-12-28 16:12:45 +0100
commit509da7ed1a1e27066451f57868108b473cf516a0 (patch)
treee8e000ec13040103d0c41e63ccceb66390330bfa /tests/arch
parent436fea9e6990c66369d7c30b571920ae115efb44 (diff)
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Revert "Fix xilinx tests, when iopads are default"
This reverts commit 477e43d921d204c6bc6403109fea6506802c948c.
Diffstat (limited to 'tests/arch')
-rw-r--r--tests/arch/xilinx/add_sub.ys2
-rw-r--r--tests/arch/xilinx/adffs.ys8
-rw-r--r--tests/arch/xilinx/bug1460.ys2
-rw-r--r--tests/arch/xilinx/counter.ys2
-rw-r--r--tests/arch/xilinx/dffs.ys4
-rw-r--r--tests/arch/xilinx/dsp_fastfir.ys2
-rw-r--r--tests/arch/xilinx/fsm.ys2
-rw-r--r--tests/arch/xilinx/latches.ys6
-rw-r--r--tests/arch/xilinx/logic.ys2
-rw-r--r--tests/arch/xilinx/lutram.ys14
-rw-r--r--tests/arch/xilinx/macc.ys4
-rw-r--r--tests/arch/xilinx/mul.ys2
-rw-r--r--tests/arch/xilinx/mul_unsigned.ys2
-rw-r--r--tests/arch/xilinx/mux.ys8
-rw-r--r--tests/arch/xilinx/shifter.ys2
-rw-r--r--tests/arch/xilinx/xilinx_dffopt.ys18
16 files changed, 40 insertions, 40 deletions
diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys
index 920717a3d..9dbddce47 100644
--- a/tests/arch/xilinx/add_sub.ys
+++ b/tests/arch/xilinx/add_sub.ys
@@ -7,5 +7,5 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 14 t:LUT2
select -assert-count 6 t:MUXCY
select -assert-count 8 t:XORCY
-select -assert-none t:LUT2 t:MUXCY t:XORCY t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D
diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys
index ba9ddf90f..c0ff6a2e2 100644
--- a/tests/arch/xilinx/adffs.ys
+++ b/tests/arch/xilinx/adffs.ys
@@ -9,7 +9,7 @@ cd adff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDCE
-select -assert-none t:BUFG t:FDCE t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDCE %% t:* %D
design -load read
@@ -22,7 +22,7 @@ select -assert-count 1 t:BUFG
select -assert-count 1 t:FDCE
select -assert-count 1 t:INV
-select -assert-none t:BUFG t:FDCE t:INV t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDCE t:INV %% t:* %D
design -load read
@@ -34,7 +34,7 @@ cd dffs # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDSE
-select -assert-none t:BUFG t:FDSE t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDSE %% t:* %D
design -load read
@@ -47,4 +47,4 @@ select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE_1
select -assert-count 1 t:INV
-select -assert-none t:BUFG t:FDRE_1 t:INV t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D
diff --git a/tests/arch/xilinx/bug1460.ys b/tests/arch/xilinx/bug1460.ys
index 73fb662dc..2018071cc 100644
--- a/tests/arch/xilinx/bug1460.ys
+++ b/tests/arch/xilinx/bug1460.ys
@@ -31,4 +31,4 @@ EOT
synth_xilinx
cd register_file
select -assert-count 32 t:RAM32M
-select -assert-none t:* t:BUFG %d t:IBUF %d t:OBUF %d t:RAM32M %d
+select -assert-none t:* t:BUFG %d t:RAM32M %d
diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys
index e4217bbaf..604acdbfc 100644
--- a/tests/arch/xilinx/counter.ys
+++ b/tests/arch/xilinx/counter.ys
@@ -11,4 +11,4 @@ select -assert-count 8 t:FDCE
select -assert-count 1 t:INV
select -assert-count 7 t:MUXCY
select -assert-count 8 t:XORCY
-select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDCE t:INV t:MUXCY t:XORCY %% t:* %D
diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys
index b2cb70323..0bba4858f 100644
--- a/tests/arch/xilinx/dffs.ys
+++ b/tests/arch/xilinx/dffs.ys
@@ -9,7 +9,7 @@ cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
-select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE %% t:* %D
design -load read
@@ -21,5 +21,5 @@ cd dffe # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
-select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE %% t:* %D
diff --git a/tests/arch/xilinx/dsp_fastfir.ys b/tests/arch/xilinx/dsp_fastfir.ys
index 05e1785d8..0067a822b 100644
--- a/tests/arch/xilinx/dsp_fastfir.ys
+++ b/tests/arch/xilinx/dsp_fastfir.ys
@@ -66,4 +66,4 @@ EOT
synth_xilinx
cd fastfir_dynamictaps
select -assert-count 2 t:DSP48E1
-select -assert-none t:* t:DSP48E1 %d t:BUFG %d t:IBUF %d t:OBUF %d
+select -assert-none t:* t:DSP48E1 %d t:BUFG %d
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys
index d60695e2c..f03400fe7 100644
--- a/tests/arch/xilinx/fsm.ys
+++ b/tests/arch/xilinx/fsm.ys
@@ -16,4 +16,4 @@ select -assert-count 1 t:FDSE
select -assert-count 1 t:LUT2
select -assert-count 3 t:LUT5
select -assert-count 1 t:LUT6
-select -assert-none t:BUFG t:IBUF t:OBUF t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
+select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys
index c1caea27a..c87a8e38b 100644
--- a/tests/arch/xilinx/latches.ys
+++ b/tests/arch/xilinx/latches.ys
@@ -8,7 +8,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
-select -assert-none t:LDCE t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LDCE %% t:* %D
design -load read
@@ -20,7 +20,7 @@ cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
select -assert-count 1 t:INV
-select -assert-none t:LDCE t:INV t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LDCE t:INV %% t:* %D
design -load read
@@ -32,4 +32,4 @@ cd latchsr # Constrain all select calls below inside the top module
select -assert-count 1 t:LDCE
select -assert-count 2 t:LUT3
-select -assert-none t:LDCE t:LUT3 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LDCE t:LUT3 %% t:* %D
diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys
index 2372cca61..d5b5c1a37 100644
--- a/tests/arch/xilinx/logic.ys
+++ b/tests/arch/xilinx/logic.ys
@@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:INV
select -assert-count 6 t:LUT2
select -assert-count 2 t:LUT4
-select -assert-none t:INV t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:INV t:LUT2 t:LUT4 %% t:* %D
diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys
index 951517fa9..6c9d1eae1 100644
--- a/tests/arch/xilinx/lutram.ys
+++ b/tests/arch/xilinx/lutram.ys
@@ -14,7 +14,7 @@
#select -assert-count 1 t:BUFG
#select -assert-count 8 t:FDRE
#select -assert-count 8 t:RAM16X1D
-#select -assert-none t:BUFG t:FDRE t:RAM16X1D t:IBUF t:OBUF %% t:* %D
+#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
design -reset
@@ -34,7 +34,7 @@ cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
select -assert-count 8 t:RAM32X1D
-select -assert-none t:BUFG t:FDRE t:RAM32X1D t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D
design -reset
@@ -54,7 +54,7 @@ cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
select -assert-count 8 t:RAM64X1D
-select -assert-none t:BUFG t:FDRE t:RAM64X1D t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
design -reset
@@ -74,7 +74,7 @@ cd lutram_1w3r
select -assert-count 1 t:BUFG
select -assert-count 24 t:FDRE
select -assert-count 4 t:RAM32M
-select -assert-none t:BUFG t:FDRE t:RAM32M t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
design -reset
@@ -94,7 +94,7 @@ cd lutram_1w3r
select -assert-count 1 t:BUFG
select -assert-count 24 t:FDRE
select -assert-count 8 t:RAM64M
-select -assert-none t:BUFG t:FDRE t:RAM64M t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
design -reset
@@ -114,7 +114,7 @@ cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 1 t:RAM32M
-select -assert-none t:BUFG t:FDRE t:RAM32M t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
design -reset
@@ -134,4 +134,4 @@ cd lutram_1w1r
select -assert-count 1 t:BUFG
select -assert-count 6 t:FDRE
select -assert-count 2 t:RAM64M
-select -assert-none t:BUFG t:FDRE t:RAM64M t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys
index 0869a8dae..11e959976 100644
--- a/tests/arch/xilinx/macc.ys
+++ b/tests/arch/xilinx/macc.ys
@@ -12,7 +12,7 @@ cd macc # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:DSP48E1
-select -assert-none t:BUFG t:FDRE t:DSP48E1 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D
design -load read
hierarchy -top macc2
@@ -29,4 +29,4 @@ select -assert-count 1 t:DSP48E1
select -assert-count 1 t:FDRE
select -assert-count 1 t:LUT2
select -assert-count 40 t:LUT3
-select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D
diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys
index 100de6629..d76814966 100644
--- a/tests/arch/xilinx/mul.ys
+++ b/tests/arch/xilinx/mul.ys
@@ -6,4 +6,4 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:DSP48E1
-select -assert-none t:DSP48E1 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:DSP48E1 %% t:* %D
diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys
index 59ead5cda..62495b90c 100644
--- a/tests/arch/xilinx/mul_unsigned.ys
+++ b/tests/arch/xilinx/mul_unsigned.ys
@@ -8,4 +8,4 @@ cd mul_unsigned # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 1 t:DSP48E1
select -assert-count 30 t:FDRE
-select -assert-none t:DSP48E1 t:FDRE t:BUFG t:IBUF t:OBUF %% t:* %D
+select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D
diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys
index faad64cc5..388272449 100644
--- a/tests/arch/xilinx/mux.ys
+++ b/tests/arch/xilinx/mux.ys
@@ -8,7 +8,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux2 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
-select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT3 %% t:* %D
design -load read
@@ -19,7 +19,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
cd mux4 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT6
-select -assert-none t:LUT6 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT6 %% t:* %D
design -load read
@@ -31,7 +31,7 @@ cd mux8 # Constrain all select calls below inside the top module
select -assert-count 1 t:LUT3
select -assert-count 2 t:LUT6
-select -assert-none t:LUT3 t:LUT6 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT3 t:LUT6 %% t:* %D
design -load read
@@ -44,4 +44,4 @@ select -assert-min 5 t:LUT6
select -assert-max 7 t:LUT6
select -assert-max 2 t:MUXF7
-select -assert-none t:LUT6 t:MUXF7 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:LUT6 t:MUXF7 %% t:* %D
diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys
index 4d63ba9c2..455437f18 100644
--- a/tests/arch/xilinx/shifter.ys
+++ b/tests/arch/xilinx/shifter.ys
@@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG
select -assert-count 8 t:FDRE
-select -assert-none t:BUFG t:FDRE t:IBUF t:OBUF %% t:* %D
+select -assert-none t:BUFG t:FDRE %% t:* %D
diff --git a/tests/arch/xilinx/xilinx_dffopt.ys b/tests/arch/xilinx/xilinx_dffopt.ys
index 5dbe11b27..dc036acfd 100644
--- a/tests/arch/xilinx/xilinx_dffopt.ys
+++ b/tests/arch/xilinx/xilinx_dffopt.ys
@@ -28,7 +28,7 @@ clean
select -assert-count 1 t:FDRE
select -assert-count 1 t:LUT6
select -assert-count 3 t:LUT2
-select -assert-none t:FDRE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D
design -load t0
@@ -39,7 +39,7 @@ clean
select -assert-count 1 t:FDRE
select -assert-count 1 t:LUT4
select -assert-count 3 t:LUT2
-select -assert-none t:FDRE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D
design -reset
@@ -74,7 +74,7 @@ clean
select -assert-count 1 t:FDSE
select -assert-count 1 t:LUT6
select -assert-count 3 t:LUT2
-select -assert-none t:FDSE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D
design -load t0
@@ -85,7 +85,7 @@ clean
select -assert-count 1 t:FDSE
select -assert-count 1 t:LUT4
select -assert-count 3 t:LUT2
-select -assert-none t:FDSE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D
design -reset
@@ -120,7 +120,7 @@ clean
select -assert-count 1 t:FDCE
select -assert-count 1 t:LUT4
select -assert-count 3 t:LUT2
-select -assert-none t:FDCE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D
design -reset
@@ -154,7 +154,7 @@ clean
select -assert-count 1 t:FDSE
select -assert-count 1 t:LUT5
select -assert-count 2 t:LUT2
-select -assert-none t:FDSE t:LUT5 t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D
design -load t0
@@ -164,7 +164,7 @@ clean
select -assert-count 1 t:FDSE
select -assert-count 2 t:LUT2
-select -assert-none t:FDSE t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDSE t:LUT2 %% t:* %D
design -reset
@@ -200,7 +200,7 @@ clean
select -assert-count 1 t:FDRSE
select -assert-count 1 t:LUT6
select -assert-count 4 t:LUT2
-select -assert-none t:FDRSE t:LUT6 t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D
design -load t0
@@ -211,6 +211,6 @@ clean
select -assert-count 1 t:FDRSE
select -assert-count 1 t:LUT4
select -assert-count 4 t:LUT2
-select -assert-none t:FDRSE t:LUT4 t:LUT2 t:IBUF t:OBUF %% t:* %D
+select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D
design -reset
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-01 23:06:02 +0000