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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-21 20:23:23 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-12-21 20:23:23 +0100 |
| commit | 436fea9e6990c66369d7c30b571920ae115efb44 (patch) | |
| tree | de332b0c4f279da1a57fbd56e7c011faa22ba832 /tests/arch | |
| parent | 1937091f622a37d8050e5cc1e7c486707fd90b2f (diff) | |
| download | yosys-436fea9e6990c66369d7c30b571920ae115efb44.tar.gz yosys-436fea9e6990c66369d7c30b571920ae115efb44.tar.bz2 yosys-436fea9e6990c66369d7c30b571920ae115efb44.zip | |
Addressed review comments
Diffstat (limited to 'tests/arch')
| -rw-r--r-- | tests/arch/xilinx/tribuf.ys | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys index 55e20c37b..eaccab126 100644 --- a/tests/arch/xilinx/tribuf.ys +++ b/tests/arch/xilinx/tribuf.ys @@ -7,7 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module -# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 2 t:IBUF select -assert-count 1 t:INV select -assert-count 1 t:OBUFT |