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| author | Miodrag Milanović <mmicko@gmail.com> | 2019-10-18 14:29:44 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-10-18 14:29:44 +0200 |
| commit | e8ef3fcdfcacbc711a4722deee95f0707634bed0 (patch) | |
| tree | 971fae1a1b7d3204827759454fa55accdc9bc01f /tests/arch/xilinx/mul.ys | |
| parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
| parent | 190b40341abd73ab5edf0e6740b6526e9575253b (diff) | |
| download | yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.tar.gz yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.tar.bz2 yosys-e8ef3fcdfcacbc711a4722deee95f0707634bed0.zip | |
Merge pull request #1454 from YosysHQ/mmicko/common_tests
Share common tests
Diffstat (limited to 'tests/arch/xilinx/mul.ys')
| -rw-r--r-- | tests/arch/xilinx/mul.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys new file mode 100644 index 000000000..d76814966 --- /dev/null +++ b/tests/arch/xilinx/mul.ys @@ -0,0 +1,9 @@ +read_verilog ../common/mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:DSP48E1 +select -assert-none t:DSP48E1 %% t:* %D |