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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
| commit | c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 (patch) | |
| tree | 79cce7951390a0068beeab26be5d310222059c51 /tests/arch/xilinx/fsm.ys | |
| parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
| download | yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.gz yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.bz2 yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.zip | |
Moved all tests in arch sub directory
Diffstat (limited to 'tests/arch/xilinx/fsm.ys')
| -rw-r--r-- | tests/arch/xilinx/fsm.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys new file mode 100644 index 000000000..a9e94c2c0 --- /dev/null +++ b/tests/arch/xilinx/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top fsm +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 5 t:FDRE +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT4 +select -assert-count 4 t:LUT6 +select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D |