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author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
commit | c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 (patch) | |
tree | 79cce7951390a0068beeab26be5d310222059c51 /tests/arch/ice40/memory.v | |
parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
download | yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.gz yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.bz2 yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.zip |
Moved all tests in arch sub directory
Diffstat (limited to 'tests/arch/ice40/memory.v')
-rw-r--r-- | tests/arch/ice40/memory.v | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/arch/ice40/memory.v b/tests/arch/ice40/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/arch/ice40/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule |