From ab8c521030a2c91a1e388d6f3c627a7f7dd525b2 Mon Sep 17 00:00:00 2001
From: Pepijn de Vos <pepijndevos@gmail.com>
Date: Mon, 11 Nov 2019 17:51:26 +0100
Subject: fix fsm test with proper clock enable polarity

---
 tests/arch/gowin/fsm.ys | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tests/arch/gowin/fsm.ys

(limited to 'tests/arch/gowin')

diff --git a/tests/arch/gowin/fsm.ys b/tests/arch/gowin/fsm.ys
new file mode 100644
index 000000000..ce4504522
--- /dev/null
+++ b/tests/arch/gowin/fsm.ys
@@ -0,0 +1,11 @@
+read_verilog ../common/fsm.v
+hierarchy -top fsm
+proc
+flatten
+
+equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check
+miter -equiv -make_assert -flatten gold gate miter
+sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter
+
+#design -load postopt
+#shell
-- 
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