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| author | Clifford Wolf <clifford@clifford.at> | 2019-11-19 17:29:27 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-11-19 17:29:27 +0100 |
| commit | 7ea0a5937ba2572f6d9d62e73e24df480c49561d (patch) | |
| tree | 7825f438b83fdc730764ba15016eeeac9eb0cf41 /tests/arch/gowin/fsm.ys | |
| parent | 15232a48af60fb7da3c3afdd144882ace2194197 (diff) | |
| parent | 8ab412eb16b1d4f98117247bf85e0c37627ee459 (diff) | |
| download | yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.tar.gz yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.tar.bz2 yosys-7ea0a5937ba2572f6d9d62e73e24df480c49561d.zip | |
Merge pull request #1449 from pepijndevos/gowin
Improvements for gowin support
Diffstat (limited to 'tests/arch/gowin/fsm.ys')
| -rw-r--r-- | tests/arch/gowin/fsm.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/arch/gowin/fsm.ys b/tests/arch/gowin/fsm.ys new file mode 100644 index 000000000..ce4504522 --- /dev/null +++ b/tests/arch/gowin/fsm.ys @@ -0,0 +1,11 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check +miter -equiv -make_assert -flatten gold gate miter +sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +#design -load postopt +#shell |