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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 12:19:59 +0200 |
| commit | 5603595e5c0efd2afc9ba810e6e5992e5d81d44c (patch) | |
| tree | dcf99c611410e055a7ea71c970938ed6ee50a3c6 /tests/arch/efinix/logic.ys | |
| parent | ab98f2dccf52a1bba396fe313ea0670603dc45ca (diff) | |
| download | yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.gz yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.tar.bz2 yosys-5603595e5c0efd2afc9ba810e6e5992e5d81d44c.zip | |
Share common tests
Diffstat (limited to 'tests/arch/efinix/logic.ys')
| -rw-r--r-- | tests/arch/efinix/logic.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys index fdedb337b..76e98e079 100644 --- a/tests/arch/efinix/logic.ys +++ b/tests/arch/efinix/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check |