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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
| commit | c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 (patch) | |
| tree | 79cce7951390a0068beeab26be5d310222059c51 /tests/arch/efinix/latches.ys | |
| parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
| download | yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.gz yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.bz2 yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.zip | |
Moved all tests in arch sub directory
Diffstat (limited to 'tests/arch/efinix/latches.ys')
| -rw-r--r-- | tests/arch/efinix/latches.ys | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/tests/arch/efinix/latches.ys b/tests/arch/efinix/latches.ys new file mode 100644 index 000000000..899d024ce --- /dev/null +++ b/tests/arch/efinix/latches.ys @@ -0,0 +1,33 @@ +read_verilog latches.v +design -save read + +hierarchy -top latchp +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D |