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authorMiodrag Milanovic <mmicko@gmail.com>2019-10-18 11:06:12 +0200
committerMiodrag Milanovic <mmicko@gmail.com>2019-10-18 11:06:12 +0200
commitc2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 (patch)
tree79cce7951390a0068beeab26be5d310222059c51 /tests/arch/ecp5/dpram.v
parent3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff)
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Moved all tests in arch sub directory
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diff --git a/tests/arch/ecp5/dpram.v b/tests/arch/ecp5/dpram.v
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+/*
+Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
+*/
+module top (din, write_en, waddr, wclk, raddr, rclk, dout);
+parameter addr_width = 8;
+parameter data_width = 8;
+input [addr_width-1:0] waddr, raddr;
+input [data_width-1:0] din;
+input write_en, wclk, rclk;
+output [data_width-1:0] dout;
+reg [data_width-1:0] dout;
+reg [data_width-1:0] mem [(1<<addr_width)-1:0]
+/* synthesis syn_ramstyle = "no_rw_check" */ ;
+always @(posedge wclk) // Write memory.
+begin
+if (write_en)
+mem[waddr] <= din; // Using write address bus.
+end
+always @(posedge rclk) // Read memory.
+begin
+dout <= mem[raddr]; // Using read address bus.
+end
+endmodule