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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-07-20 23:19:51 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-08-07 13:21:03 +0200 |
commit | 9a4f420b4b8285bd05181b6988c35ce45e3c979a (patch) | |
tree | 666157812aec1784c97967295716c636b1374d16 /tests/arch/anlogic/dffs.ys | |
parent | c39ebe6ae0e41cf9a84da852fa3cf9f71937a9b2 (diff) | |
download | yosys-9a4f420b4b8285bd05181b6988c35ce45e3c979a.tar.gz yosys-9a4f420b4b8285bd05181b6988c35ce45e3c979a.tar.bz2 yosys-9a4f420b4b8285bd05181b6988c35ce45e3c979a.zip |
Replace opt_rmdff with opt_dff.
Diffstat (limited to 'tests/arch/anlogic/dffs.ys')
-rw-r--r-- | tests/arch/anlogic/dffs.ys | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys index d3281ab89..deb90e051 100644 --- a/tests/arch/anlogic/dffs.ys +++ b/tests/arch/anlogic/dffs.ys @@ -15,6 +15,5 @@ proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 select -assert-count 1 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D +select -assert-none t:AL_MAP_SEQ %% t:* %D |